Patents by Inventor Mihailo M. Stojancic

Mihailo M. Stojancic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7093092
    Abstract: A mechanism is provided for efficiently storing a key and optionally additional data in an environment. A memory apparatus embodiment includes a plurality of memory banks and a conversion module. The number of memory banks is determined by at least the number of coordinates within an n-dimension format, each bank is associated to one of the coordinates within the n-dimension format. Each memory bank has at least a number of memory locations equal to the largest valid value for its associated coordinate. The conversion module converts a key into an n-dimension format, the n-dimension format defines a coordinate system where each coordinate represents a memory location within the associated memory bank. The conversion module stores the key into one memory location based on a policy which is dependent on the coordinates defined by the n-dimension format.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: August 15, 2006
    Assignee: ISIC Corporation
    Inventor: Mihailo M. Stojancic
  • Patent number: 7043515
    Abstract: Techniques are provided for performing modular arithmetic on a key composed of many bits. One circuit implementation includes a distributor, one or more lookup tables and a plurality of adders. The distributor segments the key into a plurality of partitions. Each partition is based on a polynomial expression corresponding to a fixed size key. Each of the bits contained within the partitions are routed on a partition basis to one or more lookup tables, the routed bits acting as indices into the one or more tables. The lookup tables store precomputed values based upon the polynomial expression. The outputted precomputed values from one or more lookup tables are outputted to the plurality of adders. The plurality of adders add the bits from a portion of the routed partitions and the outputted precomputed values from the one or more lookup tables to form the binary residue.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: May 9, 2006
    Assignee: ISIC Corporation
    Inventor: Mihailo M. Stojancic
  • Patent number: 7027597
    Abstract: A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption protocol. Two passes of Montgomery's method are used for a modular operation that is associated with the encryption protocol along with pre-computation of a constant based on a modulus. The modular operation may be a modular multiplication or a modular exponentiation. Modular arithmetic may be performed using the residue number system (RNS) and two RNS bases with conversions between the two RNS bases. A minimal number of register files are used for the computations along with an array of multiplier circuits and an array of modular reduction circuits. The approach described allows for high throughput for large encryption keys with a relatively small number of logical gates.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: April 11, 2006
    Assignee: Cisco Technologies, Inc.
    Inventors: Mihailo M. Stojancic, Mahesh S. Maddury, Kenneth J. Tomei
  • Patent number: 7027598
    Abstract: A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption protocol. Two passes of Montgomery's method are used for a modular operation that is associated with the encryption protocol along with pre-computation of a constant based on a modulus. The modular operation may be a modular multiplication or a modular exponentiation. Modular arithmetic may be performed using the residue number system (RNS) and two RNS bases with conversions between the two RNS bases. A minimal number of register files are used for the computations along with an array of multiplier circuits and an array of modular reduction circuits. The approach described allows for high throughput for large encryption keys with a relatively small number of logical gates.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: April 11, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: Mihailo M. Stojancic, Mahesh S. Maddury, Kenneth J. Tomei
  • Publication number: 20040205229
    Abstract: A hardware circuit implemented on a DRAM foundry is provided for finding the longest prefix key match. The hardware circuit includes the use of prefix search engines to store prefix keys. Each prefix search engine may advantageously include an n-dimension memory for fast efficient access. Each prefix search engine is preassigned to store prefix keys having a specific length. Based on the preassignment and the n-dimensional memory, the hardware circuit matches the longest prefix key stored in the prefix search engines by comparing all prefix search engines in parallel.
    Type: Application
    Filed: October 23, 2003
    Publication date: October 14, 2004
    Applicant: ISIC Corporation
    Inventor: Mihailo M. Stojancic
  • Publication number: 20040111459
    Abstract: Techniques are provided for performing modular arithmetic on a key composed of many bits. One circuit implementation includes a distributor, one or more lookup tables and a plurality of adders. The distributor segments the key into a plurality of partitions. Each partition is based on a polynomial expression corresponding to a fixed size key. Each of the bits contained within the partitions are routed on a partition basis to one or more lookup tables, the routed bits acting as indices into the one or more tables. The lookup tables store precomputed values based upon the polynomial expression. The outputted precomputed values from one or more lookup tables are outputted to the plurality of adders. The plurality of adders add the bits from a portion of the routed partitions and the outputted precomputed values from the one or more lookup tables to form the binary residue.
    Type: Application
    Filed: September 3, 2003
    Publication date: June 10, 2004
    Applicant: ISIC Corporation
    Inventor: Mihailo M. Stojancic
  • Publication number: 20040109365
    Abstract: A mechanism is provided for efficiently storing a key and optionally additional data in an environment. A memory apparatus embodiment includes a plurality of memory banks and a conversion module. The number of memory banks is determined by at least the number of coordinates within an n-dimension format, each bank is associated to one of the coordinates within the n-dimension format. Each memory bank has at least a number of memory locations equal to the largest valid value for its associated coordinate. The conversion module converts a key into an n-dimension format, the n-dimension format defines a coordinate system where each coordinate represents a memory location within the associated memory bank. The conversion module stores the key into one memory location based on a policy which is dependent on the coordinates defined by the n-dimension format.
    Type: Application
    Filed: September 3, 2003
    Publication date: June 10, 2004
    Applicant: ISIC Corporation
    Inventor: Mihailo M. Stojancic
  • Patent number: 5777679
    Abstract: A digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals with accurate expansion for various aspect ratios. This is accomplished through convolution multiplication carried out in 4-tuple parallel with 4-2 counters through a folding serial adder which creates a convolution sum of pixels of the motion compensated data stream to thereby expand the output video display to the desired aspect ratio.
    Type: Grant
    Filed: March 15, 1996
    Date of Patent: July 7, 1998
    Assignee: International Business Machines Corporation
    Inventors: Dennis Phillip Cheney, David Allen Hrusecky, Mihailo M. Stojancic