Abstract: A cylindrical solid-state battery and methods of making the same are disclosed. The battery includes a solid-state battery cell wound, wrapped or rolled around a core or itself, first and second terminals on opposite ends of the battery, and packaging between the first and second terminals, sealing the cell therein. The cell comprises a cathode current collector (CCC), a cathode on the CCC, a solid-state electrolyte on the cathode, an anode current collector (ACC) on the electrolyte, an insulation film on the ACC with an opening therein exposing the ACC, and a conductive redistribution layer in the opening and on the insulation film and a first sidewall of the cell. One of the terminals is electrically connected to the ACC through the redistribution layer, and the other terminal is electrically connected to the cathode or CCC on the opposite end of the battery.

Abstract: A solid-state battery and methods of making the same are disclosed. The battery includes a plurality of cells and first and second terminals on opposite sides/edges of the battery. Each cell includes a cathode current collector (CCC), a cathode thereon, a solid-state electrolyte, an anode current collector (ACC), a barrier/insulation film, a via/opening in the barrier/insulation film exposing the ACC, and a conductive redistribution layer on the ACC in the via/opening, on the barrier/insulation film, and on a first sidewall of each cell. The barrier/insulation film encapsulates the CCC, the cathode, the solid-state electrolyte and the ACC. The first sidewall of each cell is on one of the sides/edges of the battery. One terminal is electrically connected to each ACC through the redistribution layer, and the other is electrically connected to each cathode or CCC.

Abstract: A solid-state battery and methods of making the same are disclosed. The battery includes a plurality of cells and first and second terminals on opposite sides/edges of the battery. Each cell includes a cathode current collector (CCC), a cathode thereon, a solid-state electrolyte, an anode current collector (ACC), a moat in the cathode and the electrolyte and around the ACC, a barrier/insulation film, a via/opening in the barrier/insulation film exposing the ACC, and a conductive redistribution layer in the via/opening, in the moat, on the barrier/insulation film, and on a first sidewall of each cell. The barrier/insulation film encapsulates the CCC, the cathode, the solid-state electrolyte and the ACC. One terminal is electrically connected to each ACC through the redistribution layer, and the other is electrically connected to each cathode or CCC.

Abstract: Various applications of interconnect substrates in power management systems are described.

Abstract: Various applications of interconnect substrates in power management systems are described.

Abstract: Various applications of interconnect substrates in power management systems are described.

Abstract: A semiconductor package can include a semiconductor die having an integrated circuit, a first die surface, and an opposite second die surface. A packaging can be attached to the die and have a holder surface opposite the first die surface. A heat spreader can be configured to cover the second die surface and the packaging surface and can be attached thereto by a layer of adhesive positioned between the heat spreader and the semiconductor die. A semiconductor package array can include an array of semiconductor dies and a heat spreader configured to cover each semiconductor die. A conductive lead can be electrically connected to the integrated circuit in a semiconductor die and can extend from the first die surface. Manufacturing a semiconductor package can include applying thermally conductive adhesive to the heat spreader and placing the heat spreader proximate the semiconductor die.

Abstract: Various applications of interconnect substrates in power management systems are described.

Abstract: Various applications of interconnect substrates in power management systems are described.

Abstract: Various applications of interconnect substrates in power management systems are described.

Abstract: A semiconductor package can include a semiconductor die having an integrated circuit, a first die surface, and an opposite second die surface. A packaging can be attached to the die and have a holder surface opposite the first die surface. A heat spreader can be configured to cover the second die surface and the packaging surface and can be attached thereto by a layer of adhesive positioned between the heat spreader and the semiconductor die. A semiconductor package array can include an array of semiconductor dies and a heat spreader configured to cover each semiconductor die. A conductive lead can be electrically connected to the integrated circuit in a semiconductor die and can extend from the first die surface. Manufacturing a semiconductor package can include applying thermally conductive adhesive to the heat spreader and placing the heat spreader proximate the semiconductor die.

Abstract: Various applications of interconnect substrates in power management systems are described.

Abstract: A semiconductor package can include a semiconductor die having an integrated circuit, a first die surface, and an opposite second die surface. A packaging can be attached to the die and have a holder surface opposite the first die surface. A heat spreader can be configured to cover the second die surface and the packaging surface and can be attached thereto by a layer of adhesive positioned between the heat spreader and the semiconductor die. A semiconductor package array can include an array of semiconductor dies and a heat spreader configured to cover each semiconductor die. A conductive lead can be electrically connected to the integrated circuit in a semiconductor die and can extend from the first die surface. Manufacturing a semiconductor package can include applying thermally conductive adhesive to the heat spreader and placing the heat spreader proximate the semiconductor die.

Abstract: A semiconductor package can include a semiconductor die having an integrated circuit, a first die surface, and an opposite second die surface. A packaging can be attached to the die and have a holder surface opposite the first die surface. A heat spreader can be configured to cover the second die surface and the packaging surface and can be attached thereto by a layer of adhesive positioned between the heat spreader and the semiconductor die. A semiconductor package array can include an array of semiconductor dies and a heat spreader configured to cover each semiconductor die. A conductive lead can be electrically connected to the integrated circuit in a semiconductor die and can extend from the first die surface. Manufacturing a semiconductor package can include applying thermally conductive adhesive to the heat spreader and placing the heat spreader proximate the semiconductor die.

Abstract: An apparatus and method are described for cooling electronic components on a plug-in or other computer board placed within an enclosure. The inventive apparatus and system is capable of cooling a high power dissipating device, such as a Graphics Processing Unit and cooling individual ones of a plurality of other devices, such as memory chips, to within a specified temperature range. In one embodiment, cooling air is drawn from the edge of a plug-in card, over the GPU and is directed along and over arrays of memory chips. By directing the flow on and along the memory chips, a flow is established that maintains the chip-to-chip temperature difference to within a desired, uniform range. The invention allows for the incorporation of higher performance processors onto boards while maintaining memory chips within a temperature range that allows for predictable performance.

Abstract: An embodiment of the present invention is a method for wafer level IC packaging that includes the steps of: (a) forming compliant, conductive bumps on metalized bond pads or conductors; and (b) surrounding the compliant, conductive bumps in a supporting layer.

Abstract: An apparatus and method are described for cooling electronic components on a plug-in or other computer board placed within an enclosure. The inventive apparatus and system is capable of cooling a high power dissipating device, such as a Graphics Processing Unit and cooling individual ones of a plurality of other devices, such as memory chips, to within a specified temperature range. In one embodiment, cooling air is drawn from the edge of a plug-in card, over the GPU and is directed along and over arrays of memory chips. By directing the flow on and along the memory chips, a flow is established that maintains the chip-to-chip temperature difference to within a desired, uniform range. The invention allows for the incorporation of higher performance processors onto boards while maintaining memory chips within a temperature range that allows for predictable performance.

Abstract: An embodiment of the present invention is a method for wafer level IC packaging that includes the steps of: (a) forming compliant, conductive bumps on metalized bond pads or conductors; and (b) surrounding the compliant, conductive bumps in a supporting layer.

Abstract: An embodiment of the present invention is a method for wafer level IC packaging that includes the steps of: (a) forming conductive bumps on metalized bond pads or conductors; and (b) surrounding the conductive bumps in a supporting layer.

Abstract: An embodiment of the present invention is a method for wafer level IC packaging that includes the steps of: (a) forming compliant, conductive bumps on metalized bond pads or conductors; and (b) surrounding the compliant, conductive bumps in a supporting layer.