Abstract: A display panel can include a first area including a first plurality of subpixels, a second area including a second plurality of subpixels, and at least one light-transmitting portion between adjacent subpixels among the second plurality of subpixels. Also, a first subpixel in the first area includes a first light emitting layer, a first thin film transistor including a first channel area, and a first conductive member disposed under and overlapping with the first channel area of the first thin film transistor, and a second subpixel in the second area includes a second light emitting layer, a second thin film transistor including a second channel area, and a second conductive member disposed under and overlapping with the second channel area of the second thin film transistor. The first conductive member in the first subpixel in the first area is on a higher layer than the second conductive member.

Abstract: A display device including a display panel including a plurality of light emitting areas; a first optical electronic device located under the display panel; a second optical electronic device located under the display panel. Further, a first optical area of the display panel overlapping the first optical electronic device comprises a plurality of first light transmission areas in addition to the plurality of light emitting areas, a second optical area of the display panel overlapping the second optical electronic device comprises a plurality of second light transmission areas in addition the plurality of light emitting areas, and a third optical area of the display panel not overlapping the first and second optical electronic devices includes the plurality of light emitting areas without including the first and second light transmission areas.

Abstract: A display device including a display panel including a plurality of light emitting areas; and a first optical electronic device located under the display panel. Further, a first optical display area of the display panel overlapping the first optical electronic device comprises a plurality of first light transmission areas in addition to the light emitting areas, a non-overlapping display area of the display panel not overlapping the first optical electronic device includes the light emitting areas without including the first light transmission areas, and a plurality of first horizontal lines for controlling the light emitting areas horizontally extend across the non-overlapping display area and the first optical display area.

Abstract: A display device can include a display panel including a non-display area and a display area. The display area can include a first area, a third area surrounded by the first area, and a second area disposed between the first area and the third area. Here, at least one of the first, second, and third area can include a plurality of light emitting areas and a plurality of transmission areas. The display device can further include an optical electronic device located under, or in a lower portion of, the display panel and overlapping at least a portion of the first area included in the display area. The display panel can include a light shield layer disposed under transistors in the plurality of light emitting areas and not disposed in the plurality of transmission areas.

Abstract: A display device a display panel including a plurality of light emitting areas; a first optical electronic device located under the display panel; and a second optical electronic device located under the display panel.

Abstract: A display apparatus may include a display panel including a first area corresponding to a first resolution, a second area corresponding to a second resolution lower than the first resolution, and a third area corresponding to a third resolution lower than the second resolution, and a sensor disposed under the panel to overlap at least a portion of the third area. Pixels are disposed in the first area based on a first arrangement corresponding to a first pixel group including sub-pixels. Pixels are disposed in the second area based on a second arrangement corresponding to a second pixel group in which at least one of the sub-pixels of the first pixel group is omitted. Pixels are disposed in at least a part of the third area based on the first arrangement. A light transmittance portion is disposed in another part of the third area.

Abstract: A display panel includes pixels connected to gate lines, and a gate driver that supplies a gate signal to at least one of the gate lines and includes a plurality of stages. Each stage includes a pull-up transistor to apply a turn-on voltage of a first clock signal to an output terminal responsive to a voltage at a Q-node, a pull-down transistor to apply a turn-off voltage to the output terminal responsive to a voltage at a QB-node that holds the turn-on voltage during a period in which the output terminal is applied the turn-off voltage, and a QB-node control unit to apply the turn-on voltage to the QB-node responsive to the first clock signal and a second clock signal in reverse-phase with the first clock signal. Accordingly, a display panel may include a gate driver that can set, reset, and hold the voltage at a QB-node.

Abstract: A display panel and a method for fabricating the same are discussed. The display panel can include a first area in which pixels are disposed, and a second area in which pixels having lower pixels per inch (PPI) than the first area are disposed and a plurality of light-transmitting portions are disposed. The light-transmitting portions include circular or elliptical light-transmitting portions arranged in a zigzag pattern along a second direction crossing a first direction in the second area. Each of the pixel groups in the second area includes a second electrode, and the second electrode is removed from the light-transmitting area to expose light-transmitting portions.

Abstract: A gate driving circuit and an image display device including the gate driving circuit are provided. In some embodiments of the present disclosure, the gate driving circuit includes a plurality of stages configured to sequentially and repeatedly output a plurality of scan pulses having different pulse widths in response to a gate control signal applied from a timing controller and the plurality of stages sequentially generate the plurality of scan pulses having different pulse widths and phase-delayed in response to three-phase clock pulses among the gate control signals and sequentially supply the plurality of scan pulses to gate lines of a display panel to selectively adjust a light emission period or a color display period for each red pixel, green pixel, and blue pixel, thereby improving image quality.

Abstract: A display panel includes pixels connected to gate lines, and a gate driver that supplies a gate signal to at least one of the gate lines and includes a plurality of stages. Each stage includes a pull-up transistor to apply a turn-on voltage of a first clock signal to an output terminal responsive to a voltage at a Q-node, a pull-down transistor to apply a turn-off voltage to the output terminal responsive to a voltage at a QB-node that holds the turn-on voltage during a period in which the output terminal is applied the turn-off voltage, and a QB-node control unit to apply the turn-on voltage to the QB-node responsive to the first clock signal and a second clock signal in reverse-phase with the first clock signal. Accordingly, a display panel may include a gate driver that can set, reset, and hold the voltage at a QB-node.

Abstract: A gate driving circuit and an image display device including the gate driving circuit are provided. In some embodiments of the present disclosure, the gate driving circuit includes a plurality of stages configured to sequentially and repeatedly output a plurality of scan pulses having different pulse widths in response to a gate control signal applied from a timing controller and the plurality of stages sequentially generate the plurality of scan pulses having different pulse widths and phase-delayed in response to three-phase clock pulses among the gate control signals and sequentially supply the plurality of scan pulses to gate lines of a display panel to selectively adjust a light emission period or a color display period for each red pixel, green pixel, and blue pixel, thereby improving image quality.

Abstract: There is provided an electroluminescence display device comprising a display panel having a display area where images are displayed and a non-display area where images are not displayed, a subpixel located in the display area, and a voltage transfer part that is located in the non-display area and transfers a reference voltage to the subpixel in response to a signal applied from outside the display panel or a signal generated on the display panel.

Abstract: An organic light emitting display comprises pixels connected to gate lines, and a gate driving circuit to supply a gate signal to at least one gate line, and having stages connected to each other in a cascading way. A nth (n is a positive integer) stage of the gate driving circuit includes a Q1 node charging unit to charge a Q1 node to a turn-on voltage using first and second clock signals in reverse-phase, and a pull-up transistor to apply the turn-on voltage to an output terminal in response to a Q1 node voltage. The Q1 node charging unit includes a first charging unit to charge the Q1 node voltage to the turn-on voltage using the second clock signal; and a second charging unit to charge a Q2 node, coupled to the Q1 node, using the first clock signal in a section where the Q1 node has the turn-on voltage.

Abstract: An electroluminescent display device includes sub-pixels connected to gate lines, and a gate driver configured to supply a scan signal to at least one of the gate lines, and including stages. One of the stages includes a QB-node regulation unit configured to charge a QB-node and a QP-node to turn-on voltage by using a first gate clock signal and a second gate clock signal, and a pull-down unit configured to output a turn-off voltage in response to a voltage of the QP-node. The QB-node regulation unit includes a QP-node control part configured to invert a phase of a voltage of a Q1-node and apply the voltage of the inverted phase to the QP-node, and a QB-node control part configured to bootstrap the QP-node. Accordingly, by employing the gate driver including the QB-node regulation unit that provides a stable voltage to the QB-node and the QP-node, the reliability of the gate driver can be improved, and the bezel of the electroluminescence display device can be reduced.

Abstract: An electroluminescent display device includes sub-pixels connected to gate lines, and a gate driver configured to supply a scan signal to at least one of the gate lines, and including stages. One of the stages includes a QB-node regulation unit configured to charge a QB-node and a QP-node to turn-on voltage by using a first gate clock signal and a second gate clock signal, and a pull-down unit configured to output a turn-off voltage in response to a voltage of the QP-node. The QB-node regulation unit includes a QP-node control part configured to invert a phase of a voltage of a Q1-node and apply the voltage of the inverted phase to the QP-node, and a QB-node control part configured to bootstrap the QP-node. Accordingly, by employing the gate driver including the QB-node regulation unit that provides a stable voltage to the QB-node and the QP-node, the reliability of the gate driver can be improved, and the bezel of the electroluminescence display device can be reduced.

Abstract: A display panel includes pixels connected to gate lines, and a gate driver that supplies a gate signal to at least one of the gate lines and includes a plurality of stages. Each stage includes a pull-up transistor to apply a turn-on voltage of a first clock signal to an output terminal responsive to a voltage at a Q-node, a pull-down transistor to apply a turn-off voltage to the output terminal responsive to a voltage at a QB-node that holds the turn-on voltage during a period in which the output terminal is applied the turn-off voltage, and a QB-node control unit to apply the turn-on voltage to the QB-node responsive to the first clock signal and a second clock signal in reverse-phase with the first clock signal. Accordingly, a display panel may include a gate driver that can set, reset, and hold the voltage at a QB-node.

Abstract: An organic light emitting display comprises pixels connected to gate lines, and a gate driving circuit to supply a gate signal to at least one gate line, and having stages connected to each other in a cascading way. A nth (n is a positive integer) stage of the gate driving circuit includes a Q1 node charging unit to charge a Q1 node to a turn-on voltage using first and second clock signals in reverse-phase, and a pull-up transistor to apply the turn-on voltage to an output terminal in response to a Q1 node voltage. The Q1 node charging unit includes a first charging unit to charge the Q1 node voltage to the turn-on voltage using the second clock signal; and a second charging unit to charge a Q2 node, coupled to the Q1 node, using the first clock signal in a section where the Q1 node has the turn-on voltage.

Abstract: There is provided an electroluminescence display device comprising a display panel having a display area where images are displayed and a non-display area where images are not displayed, a subpixel located in the display area, and a voltage transfer part that is located in the non-display area and transfers a reference voltage to the subpixel in response to a signal applied from outside the display panel or a signal generated on the display panel.

Abstract: Provided is a liquid crystal display device according to an embodiment of the present disclosure. The display device includes: a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer deposited in sequence on a substrate. The first insulating layer and the second insulating layer include a one-hole bridge contact portion for exposing a part of the first metal layer and a part of the second metal layer at one time. The third metal layer is realized to be in contact with the first metal layer and the second metal layer through the one-hole bridge contact portion.

Abstract: Disclosed is a display device including features that suppresses threshold voltage variation among the oxide thin-film transistors of an array substrate and a method for manufacturing the same. The display device includes a first COG block including sub-pixels configured to receive an output signal from a first drive integrated circuit positioned in a first COG area; a second COG block including sub-pixels configured to receive an output signal from a second drive integrated circuit positioned in a second COG area; and an equipotential line extended from the first COG area to the second COG area.