Patents by Inventor Mihel Seitz
Mihel Seitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180031201Abstract: In one embodiment, an illumination device for a vehicle includes a light source operable for generating a light beam and a beam deflection unit operable for deflecting the light beam. The illumination device also includes a luminous layer element operable to be selectively illuminatable with the light beam in its planar extent using the beam deflection unit. The illumination device also includes a reflector element arranged in a manner adjoining the luminous layer element. The reflector element is configured such that the luminous layer element and the reflector element are illuminatable by the deflected light beam. The light beam impinging on the reflector element is divertable onto the luminous layer element.Type: ApplicationFiled: September 29, 2015Publication date: February 1, 2018Inventors: Mihel Seitz, Andreas Petersen
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Publication number: 20170205040Abstract: A device and a method for projecting a light pattern. The device includes a mirror array having a number of individual mirrors; a provision device designed to provide a light beam conducted onto the mirror array; a conducting device; and a light return guide device. The individual mirrors are designed to, in a first position, reflect first portions of the light impinging on the mirror array toward the conducting device, and, in a second position, to reflect second portions toward the light return guide device, according to the light pattern to be projected. The conducting device conducts the first portions for the projection of the light pattern; and the light return guide device guides the second portions back onto the mirror array.Type: ApplicationFiled: January 11, 2017Publication date: July 20, 2017Inventor: Mihel Seitz
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Publication number: 20090166318Abstract: A method of fabricating an integrated circuit includes providing a hard mask that includes at least one first layer and one second layer. An etching step is patterned using the hard mask, and a removal step is performed using an etchant in order to at least partially remove the first layer. The first layer and the second layer are configured in such a way that the first layer is etched by the etchant with a higher etch rate than the second layer.Type: ApplicationFiled: December 28, 2007Publication date: July 2, 2009Inventors: Mihel Seitz, Stephan Wege, Mirko Vogt, Juergen Voelkel
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Patent number: 7105404Abstract: The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate (1) made of silicon with a first hard mask layer (10; 10?) made of silicon oxide and an overlying second hard mask layer (15; 15?) made of silicon; providing a masking layer (30; 30?) made of silicon oxide above and laterally with respect to the second hard mask layer (15; 15?) made of silicon and above an uncovered edge region (RB) of the semiconductor substrate (1); providing a photoresist mask (25) above the masking layer (30; 30?) with openings corresponding from trenches (DT) to be formed in the semiconductor substrate (1); opening the masking layer (30; 30?) in a first plasma process using the photoresist mask (25), the edge region (RB) being covered by a shielding device (AR); opening the first hard mask layer (10; 10?) and second hard mask layer (15; 15?) in a second and third plasma process; and forming the trenches (DT) in the semiconductor substrate (1) in a fouType: GrantFiled: March 4, 2005Date of Patent: September 12, 2006Assignee: Infineon Technologies AGInventors: Mihel Seitz, Stephan Wege
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Patent number: 7034352Abstract: The methods and structures of the present invention involve providing a vertical dynamic random access memory (DRAM) cell device comprising a buried strap which can be laterally constrained, thereby maintaining freedom from cross talk, even at 6F2 scaling, in the absence of adjacent Shallow Trench Isolation (STI). The methods and structures of the present invention involve the further recognition that the STI can therefore be vertically confined, freed of any need to extend down below the level of the buried strap. The reduction of the buried strap to 1F width and the concomitant reduction in the depth of the STI together permit a significantly reduced aspect ratio, permitting critically improved manufacturability.Type: GrantFiled: February 11, 2004Date of Patent: April 25, 2006Assignee: Infineon Technologies AGInventors: Mihel Seitz, Venkatachalam C. Jaiprakash
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Patent number: 6960514Abstract: An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.Type: GrantFiled: March 18, 2004Date of Patent: November 1, 2005Assignee: International Business Machines CorporationInventors: Jochen Beintner, Rama Divakaruni, Johnathan Faltermeier, Philip L. Flaitz, Oleg Gluschenkov, Carol J. Heenan, Rajarao Jammy, Byeong Kim, Mihel Seitz, Akira Sudo, Yoichi Takegawa
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Publication number: 20050202626Abstract: The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate (1) made of silicon with a first hard mask layer (10; 10?) made of silicon oxide and an overlying second hard mask layer (15; 15?) made of silicon; providing a masking layer (30; 30?) made of silicon oxide above and laterally with respect to the second hard mask layer (15; 15?) made of silicon and above an uncovered edge region (RB) of the semiconductor substrate (1); providing a photoresist mask (25) above the masking layer (30; 30?) with openings corresponding from trenches (DT) to be formed in the semiconductor substrate (1); opening the masking layer (30; 30?) in a first plasma process using the photoresist mask (25), the edge region (RB) being covered by a shielding device (AR); opening the first hard mask layer (10; 10?) and second hard mask layer (15; 15?) in a second and third plasma process; and forming the trenches (DT) in the semiconductor substrate (1) in a fouType: ApplicationFiled: March 4, 2005Publication date: September 15, 2005Applicant: Infineon Technologies AGInventors: Mihel Seitz, Stephan Wege
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Publication number: 20050173748Abstract: The methods and structures of the present invention involve providing a vertical dynamic random access memory (DRAM) cell device comprising a buried strap which can be laterally constrained, thereby maintaining freedom from cross talk, even at 6F2 scaling, in the absence of adjacent Shallow Trench Isolation (STI). The methods and structures of the present invention involve the further recognition that the STI can therefore be vertically confined, freed of any need to extend down below the level of the buried strap. The reduction of the buried strap to 1F width and the concomitant reduction in the depth of the STI together permit a significantly reduced aspect ratio, permitting critically improved manufacturability.Type: ApplicationFiled: February 11, 2004Publication date: August 11, 2005Inventors: Mihel Seitz, Venkatachalam Jaiprakash
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Patent number: 6849496Abstract: A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel region of the access transistor, the first and second output regions of the access transistor, and a strap region connecting the second output region to the storage capacitor, to a narrow portion of the trench. The so confined second output region of the access transistor has reduced leakage to similar second output regions of adjacent memory cells. Adjacent memory cells can then be placed closer to one another without an increase in leakage and cross-talk between adjacent memory cells.Type: GrantFiled: July 11, 2003Date of Patent: February 1, 2005Assignee: Infineon Technologies AGInventors: Venkatachalam C. Jaiprakash, Mihel Seitz, Norbert Arnold
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Patent number: 6812092Abstract: A Dynamic Random Access Memory is fabricated in a semiconductor body of a first conductivity type in which there have been formed an array of memory cells which each include a trench capacitor and a vertical Insulated Gate Field Effect Transistor (IGFET). Each IGFET includes first and second output regions of a second opposite conductivity type and a gate which is separated from a surface of the semiconductor body by a gate dielectric layer. A gate electrode connected to the gate is formed using a Damascene process with insulating sidewall spacer regions being formed before the gate electrode is formed. Borderless contacts, which are self aligned, are made to the first output regions of each transistor using a Damascene process.Type: GrantFiled: December 19, 2000Date of Patent: November 2, 2004Assignee: Infineon TechnologiesInventors: Mihel Seitz, Michael Wise, Christian Dubuc
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Patent number: 6794282Abstract: A method of forming a semiconductor device includes providing a semiconductor device including a conductor formed thereon. A dielectric layer is formed over the conductor and a recess is formed in the dielectric layer by removing a portion of the dielectric layer to expose at least a portion of the conductor. A first layer of aluminum is deposited over the top surface of the dielectric, along the sidewalls of the dielectric layer and over the exposed portion of the conductor without altering the temperature of the semiconductor device. A second layer of aluminum is deposited over the first layer of aluminum at a temperature greater than about 300° C. A third layer of aluminum is deposited over the second layer of aluminum so as to completely fill the recess in the dielectric layer. The third layer of aluminum is slow deposited at a temperature greater than about 300° C.Type: GrantFiled: November 27, 2002Date of Patent: September 21, 2004Assignee: Infineon Technologies AGInventors: Thomas Goebel, Werner Robl, Rajeev Malik, Mihel Seitz
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Publication number: 20040173858Abstract: An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.Type: ApplicationFiled: March 18, 2004Publication date: September 9, 2004Inventors: Jochen Beintner, Rama Divakaruni, Johnathan Faltermeier, Philip L. Flaitz, Oleg Gluschenkov, Carol J. Heenan, Rajarao Jammy, Byeong Kim, Mihel Seitz, Akira Sudo, Yoichi Takegawa
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Patent number: 6759292Abstract: A memory cell includes: a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.Type: GrantFiled: October 30, 2002Date of Patent: July 6, 2004Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Mihel Seitz, Michael P. Chudzik, Jack A. Mandelman
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Patent number: 6746933Abstract: An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.Type: GrantFiled: October 26, 2001Date of Patent: June 8, 2004Assignee: International Business Machines CorporationInventors: Jochen Beintner, Rama Divakaruni, Johnathan Faltermeier, Philip L. Flaitz, Oleg Gluschenkov, Carol J. Heenan, Rajarao Jammy, Byeong Kim, Mihel Seitz, Akira Sudo, Yoichi Takegawa
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Publication number: 20040102001Abstract: In a process for preparing contact layer (CL) contacts for DRAM products filled with aluminum by physical vapor deposition (PVD), the improvements of increasing the process window of wafers per hour per deposition chamber and filling the contact hole without a void to obtain high aspect ratio CL contacts, comprising:Type: ApplicationFiled: November 27, 2002Publication date: May 27, 2004Applicant: Infineon Technologies North America Corp.Inventors: Thomas Goebel, Werner Robl, Rajeev Malik, Mihel Seitz
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Publication number: 20040084708Abstract: A memory cell includes: a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.Type: ApplicationFiled: October 30, 2002Publication date: May 6, 2004Applicants: Infineon Technologies North America Corp, International Business Machines CorporationInventors: Mihel Seitz, Michael P. Chudzik, Jack A. Mandelman
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Patent number: 6724054Abstract: A method for fabricating a self-aligned contact in an integrated circuit includes defining first spacer layers over the sidewalls of a pair of wordline stacks. An oxide layer is deposited over the tops of the wordline stacks, the first spacer layers and a surface of the substrate disposed between the first spacer layers. The oxide layer is removed from the first spacer layers, thereby forming a remaining oxide layer that covers the surface of the substrate disposed between the first spacer layers. Second spacer layers are formed over the first spacer layers, and which cover respective portions of the remaining oxide layer. The remaining oxide layer is removed to thereby form undercut regions. The undercut regions are substantially filled with contact material during formation of the contact.Type: GrantFiled: December 17, 2002Date of Patent: April 20, 2004Assignee: Infineon Technologies AGInventors: Woo-tag Kang, Rajeev Malik, Mihel Seitz
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Patent number: 6716734Abstract: In a method of making a W/WN/Poly-Gatestack, the improvement of providing low temperature sidewall oxidation to affect less outdiffusion of dopant implants near the surface to allow more margin in small groundrule device design for a support device, comprising: depositing a silicon layer on a substrate; forming a W-containing nitride layer on the deposited silicon; depositing a W layer on the W-containing nitride layer to form a W/WN/silicon stack; and performing a gatesidewall anodic oxidation by affecting a mask open to enable contacting W at its wafer edge and putting the gatestack on the positive potential or anode and the counter electrode on the negative potential.Type: GrantFiled: September 28, 2001Date of Patent: April 6, 2004Assignee: Infineon Technologies AGInventors: Mihel Seitz, Ravikumar Ramachandran
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Patent number: 6706634Abstract: A high density plasma deposition process for eliminating or reducing a zipper-like profile of opened-up voids in a poly trench fill by controlling separation between a transfer gate and storage node in a vertical DRAM, comprising: etching a recess or trench into poly Si of a semiconductor chip; forming a pattern of SiN liner using a mask transfer process for formation of a single sided strap design; removing the SiN liner and etching adjacent collar oxide away from a top part of the trench; depositing a high density plasma (HDP) polysilicon layer in the trench by flowing either SiH4 or SiH4+H2 in an inert ambient; employing a photoresist in the trench and removing the high density plasma polysilicon layer from a top surface of the semiconductor to avoid shorting in the gate conductor either by spinning on resist and subsequent chemical mechanical polishing or chemical mechanical downstream etchback of the polysilicon layer; and stripping the photoresist and depositing a top trench oxide by high denType: GrantFiled: September 19, 2000Date of Patent: March 16, 2004Assignee: Infineon Technologies AGInventors: Mihel Seitz, Andreas Knorr, Irene McStay
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Publication number: 20040033659Abstract: A Dynamic Random Access Memory is fabricated in a semiconductor body of a first conductivity type in which there have been formed an array of memory cells which each include a trench capacitor and a vertical Insulated Gate Field Effect Transistor (IGFET). Each IGFET includes first and second output regions of a second opposite conductivity type and a gate which is separated from a surface of the semiconductor body by a gate dielectric layer. A gate electrode connected to the gate is formed using a Damascene process with insulating sidewall spacer regions being formed before the gate electrode is formed. Borderless contacts, which are self aligned, are made to the first output regions of each transistor using a Damascene process.Type: ApplicationFiled: December 19, 2000Publication date: February 19, 2004Inventors: Mihel Seitz, Michael L. Wise, Christian Dubuc