Abstract: Several systems and methods for processing of video frames based on one or more video formats are disclosed. In an embodiment, a video processing system comprises a memory and a video engine. The memory stores a plurality of video frames, a primary set of instructions and a plurality of secondary sets of processing instructions. Each secondary set of processing instructions is associated with a video format. The video engine is loaded with the primary set of instructions and is configured to fetch one or more video frames and a secondary set of processing instructions from the memory based on the loaded primary set of instructions. The fetched secondary set of processing instructions corresponds to a video format determined for processing of the one or more video frames. The video engine performs processing of the one or more video frames based on the secondary set of processing instructions.

Abstract: In some examples, a method comprises receiving pixel data from an image capture device having a color filter, wherein the pixel data represents a portion of an image. The method further includes performing wavelet decomposition on the pixel data to produce decomposed pixel data and determining a local intensity of the pixel data. The method also includes determining a noise threshold value based on the local intensity and a noise intensity function that is based on the color filter; determining a noise value for the pixel data based on the decomposed pixel data and the noise threshold value; and correcting the pixel data based on the noise value to produce an output image.

Abstract: Arbitration and interleaving are performed with respect to memory requests in a memory controller that includes a set of interfaces, each configured to be coupled to a respective one of multiple external requestors, in which each interface receives memory requests from its associated external requestor. The memory controller further includes multiple sets of memory channel queues, one set for each interface, and multiple requestor arbitration modules, each associated with and coupled to a respective one of the multiple sets of memory channels. The memory controller further includes an interconnect coupled to the multiple requestor arbitration modules. The interconnect includes multiple external memory arbitration modules. Each of the requestor arbitration modules applies an arbitration algorithm to arbitrate among the memory requests in the associated set of memory channel queues.

Abstract: A method for error handling in a geometric correction engine (GCE) is provided that includes receiving configuration parameters by the GCE, generating, by the GCE in accordance with the configuration parameters, output blocks of an output frame based on corresponding blocks of an input frame, detecting, by the GCE, a run-time error during the generating, and reporting, by the GCE, an event corresponding to the run-time error.

Abstract: Described examples include an integrated circuit including a vector multiply unit including a plurality of multiply/accumulate nodes, in which the vector multiply unit is operable to provide an output from the multiply/accumulate nodes, a first data feeder operable to provide first data to the vector multiply unit in vector format, and a second data feeder operable to provide second data to the vector multiply unit in vector format.

Abstract: In described examples, a device includes a transmitter, a receiver, and a control circuit. The transmitter transmits a clock signal, and the receiver receives a response signal. The control circuit is coupled to the transmitter and the receiver. The control circuit causes the transmitter to transmit a first clock signal with a first clock period, and to transmit a second clock signal with a second clock period greater than the first clock period. The control circuit determines whether a first pattern of a signal responsive to the first clock signal is the same as a second pattern of a signal responsive to the second clock period. If the patterns are the same, the control circuit delays the clock signal with a delay responsive to the first clock period to generate a delayed clock signal. The receiver samples response signals using the delayed clock signal during normal operation of the device.

Abstract: System and methods are provided. An example system includes multiple peripherals including a first peripheral and a second peripheral, in which the first peripheral is associated with a first channel and a second channel; and a credential allocator circuit to generate a unique identification value for each of the first channel, the second channel and the second peripheral. The system further includes mapping circuitry to map a first function of the system to the first channel, map a second function of the system to the second channel, and map a third function of the system to the second peripheral; map each identification value generated by the credential allocator circuit to a corresponding function value and a corresponding traffic class value; and map each identification value generated by the credential allocator circuit to a corresponding address space value. A firewall of the system is initialized to recognize the identification values generated by the credential allocator circuit.

Abstract: Various disclosed embodiments relate to defective pixel detection and optimizing memory storage while carrying out defective pixel detection. An example, system for detecting defective pixels includes a memory to store threshold functions; and a defective pixel detector to apply, for each image pixel received, a select threshold function of the threshold functions to values of nearest-neighbor image pixels to obtain a threshold value; and determine, for each image pixel received, whether the image pixel is defective based on a comparison of a value of the image pixel to the threshold value. A statistics generator receives each image pixel that is determined to be defective; and determines a number of defective image pixels in a specified unit of image pixels and a location of each defective image pixel in the specified unit.

Abstract: Systems and methods for servicing read requests may include receiving a transaction from a processing unit while mirroring contents from an external memory to an on-chip RAM. Such systems and methods may monitor a progress of the mirroring and, based on the monitoring, access code or data values for the transaction from either the external memory or the on-chip RAM. Such systems and methods may further provide the code or data values to the processing unit according to the transaction. Such systems and methods may allow for execution of software before software has been fully downloaded to internal memory.

Abstract: Systems and methods for updating firmware may include using wait states to reduce or eliminate polling by an executing firmware component. An example includes dedicated firmware update hardware logic components, including a firmware update processing unit that executes firmware update code. The firmware update code may be paused between request of a hardware event and completion of a hardware event and under control of one or more of the hardware logic components. Once a hardware event has been completed, a hardware logic component may determine completion and, in response, restart execution of the firmware update code.

Abstract: Devices, systems and techniques for implementing freedom from interference (FFI) access rules. In an example, a device includes a set of primary components, a set of secondary components, and an interconnected coupled between the two sets of components. Each primary component of the set of primary components has an access identifier, among multiple access attributes, and an access attribute, among multiple access modes. Each secondary component of the set of secondary components is protected by a firewall. Each firewall is configured to specify, for each specific combination of an access identifier and access attribute, whether access to the associated secondary component is permitted and what type of access is permitted.

Abstract: An example apparatus includes: interface circuitry; and programmable circuitry configured to: obtain a set of processor instructions; select a first subset of processor instructions from the set; encrypt the first subset of processor instructions; select a second subset of processor instructions from the set; compute a plurality of message authentication codes (MACs) corresponding to the second subset of processor instructions; cause the interface circuitry to write the set of processor instructions to an external memory; and cause the interface circuitry to write a description of the first subset of processor instructions, a description of the second subset of processor instructions, and the plurality of MACs to the external memory.

Abstract: An example apparatus includes a read queue to store a first read request to access a first storage, sequencing circuitry coupled to the read queue, and prioritization circuitry coupled to the sequencing circuitry and coupled to the first storage and a second storage via a shared bus. The example sequencing circuitry is to sequence a portion of a second request to access the second storage to be interleaved with a wait interval of the first read request, the second request queued after the first read request. Additionally, the example prioritization circuitry is to generate a first transaction to access the first storage over the shared bus and a second transaction to access the second storage over the shared bus concurrently with the first transaction, the first transaction based on the first read request, the second transaction based on the second request.

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

Abstract: A video decoder system, in one embodiment, includes one or more processors and a memory storing instructions that when executed by the one or more processors cause the video decoding system to perform an entropy decoding operation in a frame level pipelined manner on a bitstream representative of encoded video data to produce first output data, perform at least one of an inverse quantization operation or an inverse frequency transform operation in a row level pipelined manner on the first output data to produce second output data, perform a deblocking filtering operation on first input data that includes the second output data in a row level pipelined manner to produce third output data, and output a decoded video output based on the third output data.

Abstract: In an example, a method includes storing code for a first central processing unit (CPU) executing a first application in a first region of a memory, and storing code for a second CPU executing a second application in a second region of the memory. The method includes storing shared code for the first CPU and the second CPU in a third region of the memory. The method includes storing read-write data for the first CPU in a fourth region of the memory and storing read-write data for the second CPU in a fifth region of the memory. The method includes translating a first address from a first unique address space for the first CPU to a shared address space in the third region, and translating a second address from a second unique address space for the second CPU to the shared address space in the third region.

Abstract: Transaction mappers, methods and systems are provided. An example transaction mapper includes a table that associates virtual identification values with bus-device-function (BDF) values; and a firewall that receives an input-output request including a first virtual identification value of the virtual identification values, the first virtual identification value being associated with a function of an external peripheral, generates a first BDF value and a first traffic class value based on the table and the first virtual identification value, determine whether the first virtual identification value satisfies a threshold range, and determine whether to forward the input-output request to an external host device based on whether the first virtual identification value satisfies the threshold range.

Abstract: Various embodiments disclosed herein relate to defective pixel detection and correction, and more specifically to using threshold functions based on color channels to compare pixel values to threshold values. A method is provided herein that comprises identifying a color channel of an image pixel in a frame and identifying a threshold function based at least on the color channel. The method further comprises applying the threshold function to one or more nearest-neighbor values to obtain a threshold value and determining whether a corresponding sensor pixel is defective based at least on a comparison of the image pixel to the threshold value.

Abstract: A method for error handling in a geometric correction engine (GCE) is provided that includes receiving configuration parameters by the GCE, generating, by the GCE in accordance with the configuration parameters, output blocks of an output frame based on corresponding blocks of an input frame, detecting, by the GCE, a run-time error during the generating, and reporting, by the GCE, an event corresponding to the run-time error.

Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a transaction handling block that dynamically maps the most frequently accessed memory regions into faster access memory. The technique creates shadow copies of the most frequently accessed memory regions in the faster access memory, which is associated with lower latency. The regions for which shadow copies are provided are updated dynamically based on use. The technique is flexible for different memory hierarchies.