Abstract: A method and apparatus for implementing mode based skew is disclosed. In one embodiment, an IC includes a number of different functional units each coupled to receive a respective one of a number of different clock signals. One or more of the functional circuit blocks includes at least two clock-gating circuits that are coupled to receive the clock signal provided to that functional circuit block. During a scan test, a first clock-gating circuit within a functional circuit block is configured to provide a first delay to the clock signal. A second clock-gating circuit within the functional circuit block may provide a second delay to the clock signal, the second delay being different from the first.

Abstract: A method and apparatus for implementing mode based skew is disclosed. In one embodiment, an IC includes a number of different functional units each coupled to receive a respective one of a number of different clock signals. One or more of the functional circuit blocks includes at least two clock-gating circuits that are coupled to receive the clock signal provided to that functional circuit block. During a scan test, a first clock-gating circuit within a functional circuit block is configured to provide a first delay to the clock signal. A second clock-gating circuit within the functional circuit block may provide a second delay to the clock signal, the second delay being different from the first.

Abstract: A digital scan chain system having test scan has a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output. The test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry. First and second multiplexed master/slave flip-flops are directly serially connected. A clocked latch is coupled to the output of the second multiplexed master/slave flip-flop and provides the test bit output. The clocked latch is clocked only during a test mode to save power.

Abstract: A digital scan chain system having test scan has a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output. The test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry. First and second multiplexed master/slave flip-flops are directly serially connected. A clocked latch is coupled to the output of the second multiplexed master/slave flip-flop and provides the test bit output. The clocked latch is clocked only during a test mode to save power.