Patents by Inventor Mihir Shaileshbhai Doctor
Mihir Shaileshbhai Doctor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111688Abstract: A technique for servicing a memory request is disclosed. The technique includes obtaining permissions associated with a source and a destination specified by the memory request, obtaining a first set of address translations for the memory request, and executing operations for a first request, using the first set of address translations.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Omar Fakhri Ahmed, Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Jason Todd Arbaugh, Milind Baburao Kamble, Philip Ng, Xiaojian Liu
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Publication number: 20240113875Abstract: A method and apparatus for storing keys in a key storage block includes processing a key request. A first key is allocated based upon the key request. The first key is stored in the key storage block, wherein the first key is of a first size and includes a first rule.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Omar Fakhri Ahmed, Hemaprabhu Jayanna, John Traver
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Publication number: 20240106813Abstract: A method and system for distributing keys in a key distribution system includes receiving a connection for communication from a first component. A determination is made whether the first component requires a key be generated and distributed. Based upon a security mode for the communication, the key generated and distributed to the first component.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Omar Fakhri Ahmed, Hemaprabhu Jayanna, John Traver
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Publication number: 20240103897Abstract: Systems and methods are disclosed for managing diversified virtual memory by an engine. Techniques disclosed include receiving one or more request messages, each request message including a job descriptor that specifies an operation to be performed on a respective virtual memory space, processing the job descriptors by generating one or more commands for transmission to one or more virtual memory managers, and transmitting the one or more commands to the one or more virtual memory managers (VMMs) for processing.Type: ApplicationFiled: September 27, 2022Publication date: March 28, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Omar Fakhri Ahmed
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Publication number: 20230350484Abstract: A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component, and executes a process to exit the component from the reduced power state in response to the component being active.Type: ApplicationFiled: April 21, 2023Publication date: November 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Mihir Shaileshbhai Doctor, Alexander J. Branover, Benjamin Tsien, Indrani Paul, Christopher T. Weaver, Thomas J. Gibney, Stephen V. Kosonocky, John P. Petry
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Publication number: 20230315188Abstract: Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Thomas J. Gibney, Mihir Shaileshbhai Doctor, Indrani Paul, Benjamin Tsien, Stephen V. Kosonocky, John P. Petry, Christopher T. Weaver
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Publication number: 20230280819Abstract: A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.Type: ApplicationFiled: May 12, 2023Publication date: September 7, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Alexander J. Branover, Christopher T. Weaver, Benjamin Tsien, Indrani Paul, Mihir Shaileshbhai Doctor, Thomas J. Gibney, John P. Petry, Dennis Au, Oswin Hall
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Patent number: 11703937Abstract: Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.Type: GrantFiled: September 23, 2021Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Mihir Shaileshbhai Doctor, Alexander J. Branover, Benjamin Tsien, Indrani Paul, Christopher T. Weaver, Thomas J. Gibney, Stephen V. Kosonocky, John P. Petry
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Publication number: 20230205297Abstract: A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.Type: ApplicationFiled: December 27, 2021Publication date: June 29, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Thomas J. Gibney, Stephen V. Kosonocky, Mihir Shaileshbhai Doctor, John P. Petry, Indrani Paul, Benjamin Tsien, Christopher T. Weaver
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Patent number: 11662798Abstract: A disclosed technique includes transmitting data in a first buffer associated with a first display pipe to a first display associated with the first display pipe; transmitting data in a second buffer associated with a second display pipe to the first display; requesting wake-up of a memory; and refilling one or both of the first buffer and the second buffer from the memory.Type: GrantFiled: July 30, 2021Date of Patent: May 30, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Alexander J. Branover, Christopher T. Weaver, Benjamin Tsien, Indrani Paul, Mihir Shaileshbhai Doctor, Thomas J. Gibney, John P. Petry, Dennis Au, Oswin Hall
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Patent number: 11630502Abstract: A disclosed technique includes triggering a change for a first set of one or more functional elements and for a second set of one or more functional elements from a high-power state to a low-power state; saving first state of the first set of one or more functional elements via a first set of one or more save-state elements; saving second state of the second set of one or more functional elements via a second set of one or more save-state elements; powering down the first set of one or more functional elements and the second set of one or more functional elements; and transmitting the first state and the second state to a memory.Type: GrantFiled: July 30, 2021Date of Patent: April 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: John P. Petry, Alexander J. Branover, Benjamin Tsien, Christopher T. Weaver, Stephen V. Kosonocky, Indrani Paul, Thomas J. Gibney, Mihir Shaileshbhai Doctor
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Publication number: 20230095622Abstract: A method and apparatus for isolating and restoring general-purpose input/output (GPIO) pads in a computer system includes identifying GPIO pads associated with the region responsive to an entry into a power-down state of a region of a circuit. The GPIO pads are isolated from one or more external circuits. Upon exit from the power-down state, each associated GPIO pad is restored to a current value.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Indrani Paul, Benjamin Tsien, Christopher T. Weaver, John P. Petry, Mihir Shaileshbhai Doctor, Thomas J. Gibney
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Publication number: 20230101640Abstract: Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.Type: ApplicationFiled: September 23, 2021Publication date: March 30, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Mihir Shaileshbhai Doctor, Alexander J. Branover, Benjamin Tsien, Indrani Paul, Christopher T. Weaver, Thomas J. Gibney, Stephen V. Kosonocky, John P. Petry
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Publication number: 20230099399Abstract: A method and apparatus for managing a controller includes indicating, by a processor of a first device, to the controller of a second device to enter a second power state from a first power state. The controller of the second device responds to the processor of the first device with a confirmation. The processor of the first device transmits a signal to the controller of the second device to enter the second power state. Upon receiving a wake event, the controller of the second device exits the second device from the second power state to the first power state.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Christopher T. Weaver, Indrani Paul, Benjamin Tsien, Mihir Shaileshbhai Doctor, Stephen V. Kosonocky, John P. Petry, Thomas J. Gibney
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Publication number: 20230090126Abstract: Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Alexander J. Branover, Christopher T. Weaver, Indrani Paul, Mihir Shaileshbhai Doctor, John P. Petry, Stephen V. Kosonocky, Thomas J. Gibney, Jose G. Cruz, Pravesh Gupta, Chintan S. Patel
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Publication number: 20230090567Abstract: Devices and methods for cache prefetching are provided. A device is provided which comprises a quality of service (QOS) component having first assigned registers used to store data to execute a program, a plurality of non-QOS components having second assigned registers used to store data to execute the program and a power management controller, in communication with the QOS component and the non-QOS components. The power management controller is configured to issue fences for the non-QOS components when it is determined that one or more of the non-QOS components are idle, issue a fence for the QOS component when the fences for the non-QOS components are completed and enter a reduced power state when the fences for the non-QOS components and the fence for the QOS component are completed.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Alexander J. Branover, Indrani Paul, Christopher T. Weaver, Thomas J. Gibney, Stephen V. Kosonocky, John P. Petry, Mihir Shaileshbhai Doctor
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Publication number: 20230036191Abstract: A disclosed technique includes transmitting data in a first buffer associated with a first display pipe to a first display associated with the first display pipe; transmitting data in a second buffer associated with a second display pipe to the first display; requesting wake-up of a memory; and refilling one or both of the first buffer and the second buffer from the memory.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Alexander J. Branover, Christopher T. Weaver, Benjamin Tsien, Indrani Paul, Mihir Shaileshbhai Doctor, Thomas J. Gibney, John P. Petry, Dennis Au, Oswin Hall
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Publication number: 20230030985Abstract: A disclosed technique includes triggering a change for a first set of one or more functional elements and for a second set of one or more functional elements from a high-power state to a low-power state; saving first state of the first set of one or more functional elements via a first set of one or more save-state elements; saving second state of the second set of one or more functional elements via a second set of one or more save-state elements; powering down the first set of one or more functional elements and the second set of one or more functional elements; and transmitting the first state and the second state to a memory.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: John P. Petry, Alexander J. Branover, Benjamin Tsien, Christopher T. Weaver, Stephen V. Kosonocky, Indrani Paul, Thomas J. Gibney, Mihir Shaileshbhai Doctor
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Publication number: 20230031388Abstract: Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Indrani Paul, Alexander J. Branover, Thomas J. Gibney, Mihir Shaileshbhai Doctor, John P. Petry, Stephen V. Kosonocky, Christopher T. Weaver
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Publication number: 20230031295Abstract: A disclosed technique includes triggering entry into a clock bypass mode, in which a bypass clock generator provides clock signals to functional elements and a primary clock generator does not provide clock signals to functional elements; and triggering exit from the clock bypass mode, in which the bypass clock generator does not provide clock signals to the functional elements and the primary clock generator does provide clock signals to the functional elements.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Thomas J. Gibney, Alexander J. Branover, Mihir Shaileshbhai Doctor, Xiaojie He, Indrani Paul, Benjamin Tsien, John P. Petry, Pitchaiah Katari