Abstract: A DLL circuit includes: a first delay line having a first delay buffer that provides a delay corresponding to a control voltage to an input clock signal and configured to output an output clock signal via the first delay buffer; a control voltage generation unit having a phase comparator that compares phases of the input clock signal and the output clock signal, and configured to generate the control voltage based on an output of the phase comparator; a charge storage unit configured to store charges for holding the control voltage; and a drive control unit configured to output a drive control signal for stopping an operation of the phase comparator based on a determination result regarding a delay-locked state.

Abstract: A DLL circuit (110) includes a phase delay circuit (114), a selection circuit (115), a detection circuit (117), and a clock stop circuit (116). The phase delay circuit (114) generates a plurality of delayed signals having different phases according to a clock signal. The selection circuit (115) selects one of the plurality of delayed signals as an output signal according to a setting signal. The detection circuit (117) detects a timing of switching the setting signal. The clock stop circuit (116) stops input of the clock signal to the phase delay circuit (114) for a predetermined period including the timing detected by the detection circuit (117).

Abstract: A DLL circuit (110) includes a phase delay circuit (114), a selection circuit (115), a detection circuit (117), and a clock stop circuit (116). The phase delay circuit (114) generates a plurality of delayed signals having different phases according to a clock signal. The selection circuit (115) selects one of the plurality of delayed signals as an output signal according to a setting signal. The detection circuit (117) detects a timing of switching the setting signal. The clock stop circuit (116) stops input of the clock signal to the phase delay circuit (114) for a predetermined period including the timing detected by the detection circuit (117).

Abstract: In a sampling and holding, a control logic circuit connects another end of each capacitor of a DA converter to a ground potential, and outputs a sampled input analog signal from a switched amplifier to one end of a hold capacitor to hold. In a successive approximation, it controls a switched amplifier to set an output terminal thereof to a high-impedance state and the hold capacitor to connect the one end thereof to the ground potential. Then, it switches over connection of another end of each capacitor from the ground potential to a power supply voltage based on a digital value held by a successive approximation register to output an output voltage from another end of the hold capacitor to a comparator, and compares the output voltage from another end thereof with an intermediate reference voltage to obtain a digital value from the successive approximation register.

Abstract: In a sampling and holding, a control logic circuit connects another end of each capacitor of a DA converter to a ground potential, and outputs a sampled input analog signal from a switched amplifier to one end of a hold capacitor to hold. In a successive approximation, it controls a switched amplifier to set an output terminal thereof to a high-impedance state and the hold capacitor to connect the one end thereof to the ground potential. Then, it switches over connection of another end of each capacitor from the ground potential to a power supply voltage based on a digital value held by a successive approximation register to output an output voltage from another end of the hold capacitor to a comparator, and compares the output voltage from another end thereof with an intermediate reference voltage to obtain a digital value from the successive approximation register.