Patents by Inventor Miho IIZUKA

Miho IIZUKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9237282
    Abstract: According to one embodiment, a solid-state imaging device includes a pixel array and AD converting unit. In the AD converting unit, a plurality of AD converts are arranged in a horizontal direction. The pixel is configured by a small pixel group. The small pixel group is formed of a plurality of small pixels. The plurality of small pixels read out the signal charges. The small pixel group includes two or more small pixels having different optical sensitivities. The solid-state imaging device includes N AD converting units. N is the number of small pixel groups which are arranged in a vertical direction at every small pixel. N is an integer of 2 or higher.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: January 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shiroshi Kanemitsu, Atsuhiko Nunokawa, Kazuhide Sugiura, Miho Iizuka
  • Patent number: 9148595
    Abstract: According to one embodiment, a solid state imaging device includes a first image sensor, a second image sensor, and an imaging processing circuit. A plurality of photoelectric conversion units are arranged in each of the first image sensor and the second image sensor. All of the photoelectric conversion units are configured to include pixels with different charge storage times. The imaging processing circuit includes an output combining unit. The output combining unit combines outputs by the pixels with different charge storage times with respect to each of the photoelectric conversion units.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 29, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shiroshi Kanemitsu, Tatsuji Ashitani, Miho Iizuka
  • Patent number: 9083898
    Abstract: According to one embodiment, a solid-state imaging device includes a pixel array and a high dynamic range (HDR) synthesizing circuit 19. A pixel is configured as a small pixel group. The HDR synthesizing circuit 19 includes a valid pixel selecting unit 34, a sensitivity ratio correcting unit 35, and a calculation processing unit 36. The valid pixel selecting unit 34 selects one or more small pixels validating a use of a signal value in the HDR synthesis as a valid pixel from among the small pixel group. The sensitivity ratio correcting unit 35 executes sensitivity ratio correction on the signal value of each small pixel. The calculation processing unit 36 uses the signal value of the valid pixel among the signal values of the small pixels from the sensitivity ratio correcting unit 35 for a calculation for the HDR synthesis.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: July 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shiroshi Kanemitsu, Atsuhiko Nunokawa, Miho Iizuka, Makoto Monoi
  • Publication number: 20150163430
    Abstract: According to one embodiment, in the pixel array unit, pixels that accumulate photoelectrically converted electrical charge are arranged in a matrix state. The m address lines (m is an integer of two or more) are provided per row of the pixel array unit and select the pixel in a row direction. The vertical signal line transmits a pixel signal, which is read from the pixel, in a column direction.
    Type: Application
    Filed: August 29, 2014
    Publication date: June 11, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shiroshi KANEMITSU, Atsuhiko NUNOKAWA, Miho IIZUKA, Jun INAGAWA
  • Publication number: 20140240536
    Abstract: According to one embodiment, a solid-state imaging device includes a pixel array and a high dynamic range (HDR) synthesizing circuit 19. A pixel is configured as a small pixel group. The HDR synthesizing circuit 19 includes a valid pixel selecting unit 34, a sensitivity ratio correcting unit 35, and a calculation processing unit 36. The valid pixel selecting unit 34 selects one or more small pixels validating a use of a signal value in the HDR synthesis as a valid pixel from among the small pixel group. The sensitivity ratio correcting unit 35 executes sensitivity ratio correction on the signal value of each small pixel. The calculation processing unit 36 uses the signal value of the valid pixel among the signal values of the small pixels from the sensitivity ratio correcting unit 35 for a calculation for the HDR synthesis.
    Type: Application
    Filed: November 18, 2013
    Publication date: August 28, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shiroshi Kanemitsu, Atsuhiko Nunokawa, Miho Iizuka, Makoto Monoi
  • Publication number: 20140218577
    Abstract: According to one embodiment, a solid-state imaging device includes a pixel array and AD converting unit. In the AD converting unit, a plurality of AD converts are arranged in a horizontal direction. The pixel is configured by a small pixel group. The small pixel group is formed of a plurality of small pixels. The plurality of small pixels read out the signal charges. The small pixel group includes two or more small pixels having different optical sensitivities. The solid-state imaging device includes N AD converting units. N is the number of small pixel groups which are arranged in a vertical direction at every small pixel. N is an integer of 2 or higher.
    Type: Application
    Filed: July 10, 2013
    Publication date: August 7, 2014
    Inventors: Shiroshi Kanemitsu, Atsuhiko Nunokawa, Kazuhide Sugiura, Miho Iizuka
  • Publication number: 20130242087
    Abstract: According to one embodiment, a solid state imaging device includes a first image sensor, a second image sensor, and an imaging processing circuit. A plurality of photoelectric conversion units are arranged in each of the first image sensor and the second image sensor. All of the photoelectric conversion units are configured to include pixels with different charge storage times. The imaging processing circuit includes an output combining unit. The output combining unit combines outputs by the pixels with different charge storage times with respect to each of the photoelectric conversion units.
    Type: Application
    Filed: September 14, 2012
    Publication date: September 19, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shiroshi KANEMITSU, Tatsuji ASHITANI, Miho IIZUKA