Patents by Inventor Miho Iwabuchi

Miho Iwabuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7276427
    Abstract: The present invention provides a manufacturing method for an SOI wafer with a high productivity in which generation of a void is suppressed in manufacturing the SOI wafer. In a manufacturing method for an SOI wafer of the present invention in which two starting wafers are prepared, an insulating layer is formed on at least one of the two starting wafers and the one wafer is adhered to the other wafer without using an adhesive agent, the starting wafers each with no line defect on a surface thereof are used. In a manufacturing method for an SOI wafer of the present invention in which two starting wafers are prepared, an insulating layer is formed on at least one of the two starting wafers and the one wafer is adhered to the other wafer without using an adhesive agent, the starting wafers are subjected to a high temperature heat treatment in advance.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: October 2, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masashi Ichikawa, Takeshi Kobayashi, Miho Iwabuchi
  • Publication number: 20070158653
    Abstract: The present invention is a silicon single crystal grown by CZ method, wherein Cu precipitates do not exist inside the silicon single crystal, a silicon wafer produced from the silicon single crystal, wherein Cu precipitates do not exist on a surface of and inside the wafer, and an apparatus for producing a silicon single crystal according to CZ method, wherein Cu concentration in a component made of quartz to be used in a part in which a temperature in a furnace for single crystal growth is 1000° C. or more is 1 ppb or less, and Cu concentration in a component made of quartz to be used in a part in which a temperature in a furnace for single crystal growth is less than 1000° C. is 10 ppb or less, and a method for producing a silicon single crystal by using the producing apparatus. Thereby, there are provided a silicon single crystal and a silicon wafer which have extremely few crystal defects and have high quality and high yield, a producing apparatus therefor, and a producing method therefor.
    Type: Application
    Filed: January 24, 2005
    Publication date: July 12, 2007
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Makoto Iida, Toshihiko Imai, Katsuichi Sato, Miho Iwabuchi, Masahiro Kato
  • Publication number: 20060154445
    Abstract: The present invention provides a method for manufacturing an SOI wafer with high productivity in which generation of voids is suppressed in manufacturing the SOI wafer. The present invention comprises the steps of: forming an insulating layer on at least one wafer of two starting wafers; and adhering the one wafer to the other wafer without using an adhesive, wherein a PV value of a surface of the insulating layer is 1.5 nm or less.
    Type: Application
    Filed: August 21, 2003
    Publication date: July 13, 2006
    Inventor: Miho Iwabuchi
  • Publication number: 20060014330
    Abstract: The present invention provides a manufacturing method for an SOI wafer with a high productivity in which generation of a void is suppressed in manufacturing the SOI wafer. In a manufacturing method for an SOI wafer of the present invention in which two starting wafers are prepared, an insulating layer is formed on at least one of the two starting wafers and the one wafer is adhered to the other wafer without using an adhesive agent, the starting wafers each with no line defect on a surface thereof are used. In a manufacturing method for an SOI wafer of the present invention in which two starting wafers are prepared, an insulating layer is formed on at least one of the two starting wafers and the one wafer is adhered to the other wafer without using an adhesive agent, the starting wafers are subjected to a high temperature heat treatment in advance.
    Type: Application
    Filed: December 1, 2003
    Publication date: January 19, 2006
    Inventors: Masashi Ichikawa, Takeshi Kobayashi, Miho Iwabuchi
  • Patent number: 6861268
    Abstract: The present invention provides a method for inspecting a silicon wafer making it possible to identify and efficiently detect a new defect affecting a device fabricating process, a method for manufacturing a silicon wafer enabling manufacture of wafers not having the defect, a method for fabricating a semiconductor device using the silicon wafer not having this defect, and the silicon wafer not having the defect. When a silicon wafer is inspected, inspection is made for a defect having the entire defect size of 0.5 ?m or more in which microdefects gather in a colony state.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: March 1, 2005
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Miho Iwabuchi
  • Publication number: 20020155630
    Abstract: The present invention provides a method for inspecting a silicon wafer making it possible to identify and efficiently detect a new defect affecting a device fabricating process, a method for manufacturing a silicon wafer enabling manufacture of wafers not having the defect, a method for fabricating a semiconductor device using the silicon wafer not having this defect, and the silicon wafer not having the defect. When a silicon wafer is inspected, inspection is made for a defect having the entire defect size of 0.5 &mgr;m or more in which microdefects gather in a colony state.
    Type: Application
    Filed: April 24, 2002
    Publication date: October 24, 2002
    Inventor: Miho Iwabuchi