Abstract: A method is provided for controlling copper agglomeration on a substrate and for forming void-free bulk copper metal filling of recessed features in integrated circuits. In one embodiment, the method includes providing a substrate having a topography including a top surface and at least one recessed feature comprising at least a sidewall surface and a bottom surface, depositing a barrier film on the substrate topography, and depositing a metal-containing wetting film on the barrier film. The method further includes physical vapor depositing copper metal on the metal-containing wetting film, where the substrate temperature is sufficiently high to form a smooth copper metal seed layer on the metal-containing wetting film. Void-free bulk copper metal may be plated in the at least one recessed feature.

Abstract: A method is provided for void-free copper (Cu) filling of recessed features in a semiconductor device. The method includes providing a patterned substrate containing a recessed feature, depositing a barrier film on the patterned substrate, including in the recessed feature, depositing a Ru metal film on the barrier film, and depositing a discontinuous Cu seed layer on the Ru metal film, where the Cu seed layer partially covers the Ru metal film in the recessed feature. The method further includes exposing the substrate to an oxidation source gas that oxidizes the Cu seed layer and the portion of the Ru metal film not covered by the Cu seed layer, heat-treating the oxidized Cu seed layer and the oxidized Ru metal film under high vacuum conditions or in the presence of an inert gas to activate the oxidized Ru metal film for Cu plating, and filling the recessed feature with bulk Cu metal.

Abstract: A method is provided for integrating cobalt nitride cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt nitride cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k dielectric regions, and selectively forming a cobalt nitride cap layer on the Cu paths relative to the low-k dielectric regions.

Abstract: A method for integrating ruthenium (Ru) metal cap layers and modified Ru metal cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in bulk Cu metal. In one embodiment, the method includes providing a planarized patterned substrate containing a Cu metal surface and a dielectric layer surface, depositing first Ru metal on the Cu metal surface, and depositing additional Ru metal on the dielectric layer surface, where the amount of the additional Ru metal is less than the amount of the first Ru metal. The method further includes at least substantially removing the additional Ru metal from the dielectric layer surface to improve the selective formation of a Ru metal cap layer on the Cu metal surface. Other embodiments further include incorporating one or more types of modifier elements into the dielectric layer surface, the Cu metal surface, the Ru metal cap layer, or a combination thereof.

Abstract: A method for integrating low-temperature selective Ru metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in bulk Cu metal. The method includes providing a patterned substrate containing a recessed feature in a dielectric layer, where the recessed feature is at least substantially filled with planarized bulk Cu metal, heat-treating the bulk Cu metal and the dielectric layer in the presence of H2, N2, or NH3, or a combination thereof, and selectively depositing a Ru metal film on the heat-treated planarized bulk Cu metal.

Abstract: A method is provided for integrating cobalt tungsten cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt tungsten cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k regions, and forming a cobalt tungsten cap layer on the Cu paths.

Abstract: A method is provided for integrating cobalt nitride cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt nitride cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k dielectric regions, and selectively forming a cobalt nitride cap layer on the Cu paths relative to the low-k dielectric regions.

Abstract: A method is provided for integrating cobalt tungsten cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt tungsten cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k regions, and forming a cobalt tungsten cap layer on the Cu paths.

Abstract: A method for integrating ruthenium (Ru) metal cap layers and modified Ru metal cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in bulk Cu metal. In one embodiment, the method includes providing a planarized patterned substrate containing a Cu metal surface and a dielectric layer surface, depositing first Ru metal on the Cu metal surface, and depositing additional Ru metal on the dielectric layer surface, where the amount of the additional Ru metal is less than the amount of the first Ru metal. The method further includes at least substantially removing the additional Ru metal from the dielectric layer surface to improve the selective formation of a Ru metal cap layer on the Cu metal surface. Other embodiments further include incorporating one or more types of modifier elements into the dielectric layer surface, the Cu metal surface, the Ru metal cap layer, or a combination thereof.

Abstract: A method is provided for controlling copper agglomeration on a substrate and for forming void-free bulk copper metal filling of recessed features in integrated circuits. In one embodiment, the method includes providing a substrate having a topography including a top surface and at least one recessed feature comprising at least a sidewall surface and a bottom surface, depositing a barrier film on the substrate topography, and depositing a metal-containing wetting film on the barrier film. The method further includes physical vapor depositing copper metal on the metal-containing wetting film, where the substrate temperature is sufficiently high to form a smooth copper metal seed layer on the metal-containing wetting film. Void-free bulk copper metal may be plated in the at least one recessed feature.

Abstract: A method for integrating low-temperature selective Ru metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in bulk Cu metal. The method includes providing a patterned substrate containing a recessed feature in a dielectric layer, where the recessed feature is at least substantially filled with planarized bulk Cu metal, heat-treating the bulk Cu metal and the dielectric layer in the presence of H2, N2, or NH3, or a combination thereof, and selectively depositing a Ru metal film on the heat-treated planarized bulk Cu metal.

Abstract: A method is provided for void-free copper (Cu) filling of recessed features in a semiconductor device. The method includes providing a patterned substrate containing a recessed feature, depositing a barrier film on the patterned substrate, including in the recessed feature, depositing a Ru metal film on the barrier film, and depositing a discontinuous Cu seed layer on the Ru metal film, where the Cu seed layer partially covers the Ru metal film in the recessed feature. The method further includes exposing the substrate to an oxidation source gas that oxidizes the Cu seed layer and the portion of the Ru metal film not covered by the Cu seed layer, heat-treating the oxidized Cu seed layer and the oxidized Ru metal film under high vacuum conditions or in the presence of an inert gas to activate the oxidized Ru metal film for Cu plating, and filling the recessed feature with bulk Cu metal.

Abstract: An electroless plating solution includes a first liquid chemical containing a metal salt and a second liquid chemical containing a reducing agent. In respective liquid chemical supply lines, liquid chemical opening/closing units are installed in the vicinity of a junction therebetween, and at the same time, a plating solution opening/closing unit is provided in the vicinity of an discharge opening in supply line of an electroless plating solution after the first and the second liquid chemical are joined together. A plating solution in the supply line disposed between these opening/closing units corresponds to a discharge amount needed for a plating processing of about one time. Further, both of the liquid chemicals are mixed together only during the time period between the time when a plating processing on one substrate has been started and the time when a plaiting processing is to start on a following substrate.

Abstract: A plate is placed near a substrate held by a substrate holding section. A treating liquid is ejected from a treating liquid ejecting section, thereby plating the substrate electrolessly. The treating liquid flows through the gap between the substrate and the plate. Therefore a flow of the treating liquid occurs on the substrate. As a result, a fresh treating liquid can be supplied onto the substrate. Thus, a plating film can be formed very uniformly on the substrate even if the amount of treating liquid is small.

Abstract: In a method of electroless plating, catalytically active nuclei are formed on a diffusion inhibiting layer (such as a barrier layer), the catalytically active nuclei being catalytically active on a reducing agent contained in an electroless plating solution, and an electroless plating is then carried out by using the electroless plating solution. The method allows the formation of an electrolessly plated coating on a barrier layer through the acceleration of the reaction of a reducing agent contained in an electroless plating solution by catalytically active nucleus.