Abstract: A kit for making an original holder is disclosed. In the kit, a holder 10 of A4 size with a paper fastener 7 is divided into two and provided as two members 11 and 12. The member 11, consisting of a front panel 1 isolated from other portions of the holder cover, is a substantially flat paper sheet and generally rectangular in standardized lengthwise A4 size which is adapted to be passed through common personal printers easily. The member 12 consists of the rest of the holder cover and a paper fastener 7. The rest of the cover is made with a single paper sheet in which a back panel 2, a spine panel 3, a pleat 4 and a joint portion 5 are defined by folding the sheet, and the paper fastener 7 is secured on the pleat 4. A double-coated adhesive tape 6 is adhesively bonded on the outside surface of the joint portion 5 along a line a—a. Upon making the holder 10 with this kit, the member 11 is fed through a printer and any desired designs are printed thereon.

Abstract: Connection between a PMOS transistor and an NMOS transistor is made through a refractory metal salicide layer in the source and drain regions of these transistors. The salicide is low in resistance, thereby partially substituting for a first Al wiring in intracell wiring. The resulting empty area provides a wiring area and, hence, the freedom of chip layout is enhanced. Besides, in a microcell which constitutes a logic circuit, such as a gate array, lateral wiring grid dots can be utilized as a wiring area.

Abstract: A plurality of macro cell layout regions 9 in cell regions 2 on a semiconductor substrate 1 are divided into three portions in a second direction. Each of the divided portions is provided with basic circuits 14a through 14c. In each basic circuit, a first common line 16 is connected to an output node of a clock input driver 11 via a clock output line 17. A plurality of predrivers 15(1) through 15(n) have their input nodes IN connected to the first common line 16 and have their output nodes OUT connected to a second common line 18. A plurality of main drivers 19(1) through 19mhave their input nodes IN connected to the second common line 18 and have their output nodes OUT connected to a third common line 20. The third common line is connected to a plurality of clock signal supply lines 21(1) through 21(s) commonly provided to the basic circuits 14a through 14c. The clock signal supply lines 21(1) through 21(s) are connected to clock input nodes of internal circuits 22 each requiring a clock signal.

Abstract: A clock driver circuit is furnished in a centrally located macro cell layout region. The clock driver circuit has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a first and a second common line, and the input and output nodes of the main drivers are short-circuited by the second and a third common line. A plurality of clock driver circuits are formed predetermined distances apart and arranged to intersect the clock driver circuit perpendicularly. Each of the clock driver circuits has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a fourth and a fifth common line, and the input and output nodes of the main drivers are short-circuited by the fifth and a sixth common line. The third and the fourth common lines are interconnected.

Abstract: An apparatus and method for checking logic circuit checks logic element influenced by hot carriers in the logic circuit. The present invention comprises means for measuring rising transition time t.sub.r (or falling transition time t.sub.f) of signal generated by logic element comprising one portion of the logic circuit; means for calculating a ratio (DUTY) of rising transition time t.sub.r (or falling transition time t.sub.f) and operation period T of the signal; and means for comparing said DUTY with maximum allowable duty (DUTYMAX), in order to detect the logic element having DUTY exceeding maximum allowable duty (DUTYMAX).

Abstract: In order to lay out a driver circuit having high drivability without increasing a semiconductor chip area, a macro cell (22) such as a clock driver having a large fan-out is arranged under a feeder line (20). It is possible to feed the macro cell (22) from the feeder line (20), which is a second layer aluminum wire, in a short distance. An input signal line (23) and an output signal line (24) which are connected to input and output pins of the macro cell (22) are provided in positions not to be in contact with the feeder line (20). Since the macro cell (22) is arranged in a portion of an internal region which is located under the feeder line (20), it is possible to suppress increase of the layout area as well as electromigration caused by feeding to the macro cell (22).

Abstract: In order to lay out a driver circuit having high drivability without increasing a semiconductor chip area, a macro cell (22) such as a clock driver having a large fan-out is arranged under a feeder line (20). It is possible to feed the macro cell (22) from the feeder line (20), which is a second layer aluminum wire, in a short distance. An input signal line (23) and an output signal line (24) which are connected to input and output pins of the macro cell (22) are provided in positions not to be in contact with the feeder line (20). Since the macro cell (22) is arranged in a portion of an internal region which is located under the feeder line (20), it is possible to suppress increase of the layout area as well as electromigration caused by feeding to the macro cell (22).