Patents by Inventor Mihoko Akiyama
Mihoko Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10121541Abstract: The present invention makes it possible to form a circuit configuration that is capable of executing a keyword search at an increased speed while suppressing an increase in the memory capacity of a content-addressable memory. A semiconductor device according to an aspect of the present invention searches an input data string for a predesignated keyword, and includes a first content-addressable memory that stores a partial keyword corresponding to a predetermined number of data beginning with the first data of the keyword, a second content-addressable memory that stores the entirety of the keyword, and a control circuit that is coupled to the first content-addressable memory and to the second content-addressable memory. When a portion matching the partial keyword is detected in the input data string by a search in the first content-addressable memory, the second content-addressable memory executes a search on search data extracted from the input data string.Type: GrantFiled: August 4, 2016Date of Patent: November 6, 2018Assignee: Renesas Electronics CorporationInventors: Futoshi Igaue, Kenji Yoshinaga, Naoya Watanabe, Mihoko Akiyama
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Patent number: 9620214Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: GrantFiled: April 20, 2015Date of Patent: April 11, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
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Publication number: 20170060438Abstract: The present invention makes it possible to form a circuit configuration that is capable of executing a keyword search at an increased speed while suppressing an increase in the memory capacity of a content-addressable memory. A semiconductor device according to an aspect of the present invention searches an input data string for a predesignated keyword, and includes a first content-addressable memory that stores a partial keyword corresponding to a predetermined number of data beginning with the first data of the keyword, a second content-addressable memory that stores the entirety of the keyword, and a control circuit that is coupled to the first content-addressable memory and to the second content-addressable memory. When a portion matching the partial keyword is detected in the input data string by a search in the first content-addressable memory, the second content-addressable memory executes a search on search data extracted from the input data string.Type: ApplicationFiled: August 4, 2016Publication date: March 2, 2017Inventors: Futoshi IGAUE, Kenji YOSHINAGA, Naoya WATANABE, Mihoko AKIYAMA
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Patent number: 9159376Abstract: A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage of a match line MLA. A match amplifier B determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array B, according to a voltage of a match line MLB. A block-B control circuit directs to start searching in the memory array B after two cycles after searching has been started in the memory array A. A block-B activation control circuit directs to stop searching in the memory array B according to a voltage of the match line MLA after searching in the memory array A.Type: GrantFiled: June 13, 2014Date of Patent: October 13, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Mihoko Akiyama
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Publication number: 20150228341Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: April 20, 2015Publication date: August 13, 2015Inventors: Naoya WATANABE, Isamu HAYASHI, Teruhiko AMANO, Fukashi MORISHITA, Kenji YOSHINAGA, Mihoko AKIYAMA, Shinya MIYAZAKI, Masakazu ISHIBASHI, Katsumi DOSAKA
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Patent number: 9042148Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: GrantFiled: January 9, 2014Date of Patent: May 26, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
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Publication number: 20140313807Abstract: A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage of a match line MLA. A match amplifier B determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array B, according to a voltage of a match line MLB. A block-B control circuit directs to start searching in the memory array B after two cycles after searching has been started in the memory array A. A block-B activation control circuit directs to stop searching in the memory array B according to a voltage of the match line MLA after searching in the memory array A.Type: ApplicationFiled: June 13, 2014Publication date: October 23, 2014Inventor: Mihoko AKIYAMA
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Patent number: 8780599Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputing an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.Type: GrantFiled: March 1, 2013Date of Patent: July 15, 2014Assignee: Renesas Electronics CorporationInventor: Mihoko Akiyama
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Publication number: 20140126264Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: January 9, 2014Publication date: May 8, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Naoya WATANABE, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
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Patent number: 8638583Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: GrantFiled: September 15, 2012Date of Patent: January 28, 2014Assignee: Renesas Electronics CorporationInventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
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Patent number: 8638599Abstract: A semiconductor storage device has tunnel magnetoresistive elements in memory cells. The array includes a memory array having a plurality of memory cells; a plurality of read-word-lines and a plurality of write-word-lines; a plurality of read-bit-lines; a plurality of first write-bit-lines and a plurality of second write-bit-lines; a first driver; a read circuit; a second driver; and a write circuit. The memory cell has a mos transistor, of which one current electrode is coupled to the read-bit-line. A tunnel magnetoresistive element is coupled between a control electrode of the mos transistor and the read-word-line. A capacitive element is coupled to the tunnel magnetoresistive element and forms an RC circuit together with the tunnel magnetoresistive element.Type: GrantFiled: December 17, 2012Date of Patent: January 28, 2014Assignee: Renesas Electronics CorporationInventor: Mihoko Akiyama
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Patent number: 8599639Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.Type: GrantFiled: May 22, 2013Date of Patent: December 3, 2013Assignee: Renesas Electronics CorporationInventors: Mihoko Akiyama, Futoshi Igaue, Kenji Yoshinaga, Masashi Matsumura, Fukashi Morishita
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Publication number: 20130249624Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.Type: ApplicationFiled: May 22, 2013Publication date: September 26, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Mihoko AKIYAMA, Futoshi IGAUE, Kenji YOSHINAGA, Masashi MATSUMURA, Fukashi MORISHITA
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Patent number: 8451678Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.Type: GrantFiled: April 5, 2011Date of Patent: May 28, 2013Assignee: Renesas Electronics CorporationInventors: Mihoko Akiyama, Futoshi Igaue, Kenji Yoshinaga, Masashi Matsumura, Fukashi Morishita
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Patent number: 8400803Abstract: A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage of a match line MLA. A match amplifier B determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array B, according to a voltage of a match line MLB. A block-B control circuit directs to start searching in the memory array B after two cycles after searching has been started in the memory array A. A block-B activation control circuit directs to stop searching in the memory array B according to a voltage of the match line MLA after searching in the memory array A.Type: GrantFiled: March 2, 2011Date of Patent: March 19, 2013Assignee: Renesas Electronics CorporationInventor: Mihoko Akiyama
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Publication number: 20130010513Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: September 15, 2012Publication date: January 10, 2013Inventors: Naoya WATANABE, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
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Patent number: 8310852Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: GrantFiled: March 13, 2012Date of Patent: November 13, 2012Assignee: Renesas Electronics CorporationInventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
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Publication number: 20120170344Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: March 13, 2012Publication date: July 5, 2012Applicant: Renesas Electronics CorporationInventors: Naoya WATANABE, Isamu HAYASHI, Teruhiko AMANO, Fukashi MORISHITA, Kenji YOSHINAGA, Mihoko AKIYAMA, Shinya MIYAZAKI, Masakazu ISHIBASHI, Katsumi DOSAKA
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Patent number: 8164934Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: GrantFiled: March 9, 2010Date of Patent: April 24, 2012Assignee: Renesas Electronics CorporationInventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
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Publication number: 20110216569Abstract: A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage of a match line MLA. A match amplifier B determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array B, according to a voltage of a match line MLB. A block-B control circuit directs to start searching in the memory array B after two cycles after searching has been started in the memory array A. A block-B activation control circuit directs to stop searching in the memory array B according to a voltage of the match line MLA after searching in the memory array A.Type: ApplicationFiled: March 2, 2011Publication date: September 8, 2011Inventor: Mihoko AKIYAMA