Patents by Inventor Mihoko Wada

Mihoko Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150003138
    Abstract: There is a need to highly integrate a circuit area of content addressable memory (CAM) and ensure faster operation thereof. A priority encoder and row decoder portion shares a row address register including more than one row. Each row of the row address register corresponds to each entry of a TCAM array mat and retains each address. Each row of the row address register corresponds to each word line and match line of the TCAM array mat. Writing data to the TCAM array mat activates word line for a row retained in the row address register corresponding to a specified address. Searching for the TCAM array mat activates a match line for the TCAM array mat. The row address register for the corresponding row stores the address of an entry for the TCAM array mat matching search data.
    Type: Application
    Filed: September 16, 2014
    Publication date: January 1, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Mihoko WADA
  • Patent number: 8891272
    Abstract: There is a need to highly integrate a circuit area of content addressable memory (CAM) and ensure faster operation thereof. A priority encoder and row decoder portion shares a row address register including more than one row. Each row of the row address register corresponds to each entry of a TCAM array mat and retains each address. Each row of the row address register corresponds to each word line and match line of the TCAM array mat. Writing data to the TCAM array mat activates word line for a row retained in the row address register corresponding to a specified address. Searching for the TCAM array mat activates a match line for the TCAM array mat. The row address register for the corresponding row stores the address of an entry for the TCAM array mat matching search data.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: November 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Mihoko Wada
  • Patent number: 8725968
    Abstract: A storage section controlling apparatus includes a queuing section adapted to retain a processing order of write requests and readout requests from a data processing apparatus to plural storage sections to, and a processing order controlling section adapted to change, where a readout request for a target region of a duplexing process of a second storage section of the plural storage sections by a duplexing controlling section is issued from the data processing apparatus and a write request for a target region of at least one first storage section of the plural storage sections of a copying source corresponding to the target region of the readout request exists later than a processing turn of the readout request in a processing order in the queuing section, the processing turn of the readout request in the processing order so as to be later than the writing request in the processing order.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: May 13, 2014
    Assignee: Fujitsu Limited
    Inventor: Mihoko Wada
  • Publication number: 20130242632
    Abstract: There is a need to highly integrate a circuit area of content addressable memory (CAM) and ensure faster operation thereof. A priority encoder and row decoder portion shares a row address register including more than one row. Each row of the row address register corresponds to each entry of a TCAM array mat and retains each address. Each row of the row address register corresponds to each word line and match line of the TCAM array mat. Writing data to the TCAM array mat activates word line for a row retained in the row address register corresponding to a specified address. Searching for the TCAM array mat activates a match line for the TCAM array mat. The row address register for the corresponding row stores the address of an entry for the TCAM array mat matching search data.
    Type: Application
    Filed: December 11, 2012
    Publication date: September 19, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Mihoko WADA
  • Patent number: 8347051
    Abstract: A storage apparatus includes a second volume which stores data serving as a copying source of data to be stored in a first volume, serving as a data copying destination in another storage apparatus, a session establishing unit which establishes a session between the second volume and the first volume, and a copy directing unit which directs a volume, including a free area, in the other storage apparatus such that data equivalent to the data to be stored in the first volume is copied, in response to a copy setting command issued by a server.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: January 1, 2013
    Assignee: Fujitsu Limited
    Inventor: Mihoko Wada
  • Patent number: 8281097
    Abstract: A storage device includes storage units, a management section that manages a logically defined storage area as a real logical volume by associating the storage area with a physical storage area created using the storage units in advance and manages the logically defined storage area as a virtual logical volume by associating the storage area with a physical storage area when data is added, a determination section that determines whether the activity ratio of the virtual logical volume exceeds a threshold and whether the physical storage area associated with a storage area of the virtual logical volume is managed by another control unit, and a migration section that migrates data stored in the virtual logical volume to a real logical volume when the activity ratio exceeds the threshold and the physical storage area associated with the storage area of the virtual logical volume managed by another control unit.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: October 2, 2012
    Assignee: Fujitsu Limited
    Inventor: Mihoko Wada
  • Patent number: 7945749
    Abstract: A copy source device includes bit map acquisition and bit map merge functions. In accordance with bit-map management information in which a bit map indicating the presence of written data is rounded, the bit map acquisition and bit map merger acquires required bit map from a copy destination device, and merges the acquired bit map to a corresponding bit map of the copy source device. The copy destination device includes bit-map management information updater. The bit-map management information updater updates bit-map management information indicating a write operation when the write operation has been performed during a copy suspend mode. During a copy resume mode, the copy source device requests the copy destination device to transfer the bit-map management information, and in response, the copy destination device transfers the bit-map management information.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: May 17, 2011
    Assignee: Fujitsu Limited
    Inventors: Yoshinari Shinozaki, Hideaki Omura, Koji Uchida, Mihoko Wada
  • Publication number: 20100332778
    Abstract: A storage device includes storage units, a management section that manages a logically defined storage area as a real logical volume by associating the storage area with a physical storage area created using the storage units in advance and manages the logically defined storage area as a virtual logical volume by associating the storage area with a physical storage area when data is added, a determination section that determines whether the activity ratio of the virtual logical volume exceeds a threshold and whether the physical storage area associated with a storage area of the virtual logical volume is managed by another control unit, and a migration section that migrates data stored in the virtual logical volume to a real logical volume when the activity ratio exceeds the threshold and the physical storage area associated with the storage area of the virtual logical volume managed by another control unit.
    Type: Application
    Filed: June 3, 2010
    Publication date: December 30, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Mihoko Wada
  • Publication number: 20100169596
    Abstract: A storage apparatus includes a second volume which stores data serving as a copying source of data to be stored in a first volume, serving as a data copying destination in another storage apparatus, a session establishing unit which establishes a session between the second volume and the first volume, and a copy directing unit which directs a volume, including a free area, in the other storage apparatus such that data equivalent to the data to be stored in the first volume is copied, in response to a copy setting command issued by a server.
    Type: Application
    Filed: December 15, 2009
    Publication date: July 1, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Mihoko Wada
  • Publication number: 20100115219
    Abstract: A storage section controlling apparatus includes a queuing section adapted to retain a processing order of write requests and readout requests from a data processing apparatus to plural storage sections to, and a processing order controlling section adapted to change, where a readout request for a target region of a duplexing process of a second storage section of the plural storage sections by a duplexing controlling section is issued from the data processing apparatus and a write request for a target region of at least one first storage section of the plural storage sections of a copying source corresponding to the target region of the readout request exists later than a processing turn of the readout request in a processing order in the queuing section, the processing turn of the readout request in the processing order so as to be later than the writing request in the processing order.
    Type: Application
    Filed: January 13, 2010
    Publication date: May 6, 2010
    Inventor: Mihoko Wada
  • Publication number: 20070146788
    Abstract: A copy source device includes bit map acquisition and bit map merge functions. In accordance with bit-map management information in which a bit map indicating the presence of written data is rounded, the bit map acquisition and bit map merger acquires required bit map from a copy destination device, and merges the acquired bit map to a corresponding bit map of the copy source device. The copy destination device includes bit-map management information updater. The bit-map management information updater updates bit-map management information indicating a write operation when the write operation has been performed during a copy suspend mode. During a copy resume mode, the copy source device requests the copy destination device to transfer the bit-map management information, and in response, the copy destination device transfers the bit-map management information.
    Type: Application
    Filed: September 29, 2006
    Publication date: June 28, 2007
    Applicant: Fujitsu Limited
    Inventors: Yoshinari Shinozaki, Hideaki Omura, Koji Uchida, Mihoko Wada
  • Publication number: 20060212669
    Abstract: The present invention provides a control method for a storage system comprising the first process for copying information stored by a first storage apparatus which is accessed by an upper echelon apparatus to a second storage apparatus, the second process for judging whether or not storage contents of the first and second storage apparatuses are identical when a fault occurs in the first storage apparatus, and the third process for controlling so that the upper echelon apparatus accesses the second storage apparatus in place of the first storage apparatus if the storage contents of the first and second storage apparatuses are identical.
    Type: Application
    Filed: September 30, 2005
    Publication date: September 21, 2006
    Applicant: Fujitsu Limited
    Inventors: Koji Uchida, Hideaki Ohmura, Yoshinari Shinozaki, Mihoko Wada