Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.

Abstract: A method includes following steps. A first precursor is pulsed over a substrate such that first precursor adsorbs on a first region and a second region of the substrate. A first plurality of the first precursor adsorbing on the first region is then removed using a plasma, while leaving a second plurality of the first precursor adsorbing on the second region. A second precursor is then pulsed to the substrate to form a monolayer of a film on the second region and a material on the first region. The material is then removed using a plasma. The substrate is biased during removing the material.

Abstract: A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.

Abstract: A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.

Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.

Abstract: Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.

Abstract: A semiconductor device includes a plurality of semiconductor layers arranged one above another, and source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers. The semiconductor device further includes a gate structure surrounding each of the plurality of semiconductor layers. The gate structure includes interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer. The gate structure further includes gate spacers spacing apart the gate structure from the source/drain epitaxial regions. A top position of the high-k dielectric layer is lower than top positions of the gate spacers.

Abstract: Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.

Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a gate dielectric layer over a semiconductor substrate; depositing a work function layer over the gate dielectric layer by an atomic layer deposition (ALD) process, wherein the work function layer comprises a metal element and a nonmetal element, and the ALD process comprises a plurality of cycles. Each of the cycles comprises: introducing a precursor gas comprising the metal element to a chamber to form a precursor surface layer on the semiconductor substrate in the chamber; purging a remaining portion of the precursor gas away from the chamber; performing a reactive-gas plasma treatment using a reactive-gas plasma comprising the nonmetal element to convert the precursor surface layer into a monolayer of the work function layer; purging a remaining portion of the reactive-gas plasma away from the chamber, and performing an inert-gas plasma treatment in the chamber.

Abstract: A semiconductor device includes source and a drain above a substrate and spaced apart along a first direction, and a semiconductor channel extending between the source and the drain. The semiconductor device further includes gate spacers, an interfacial layer, and a metal gate structure. The gate spacers are disposed on the semiconductor channel and spaced apart by a spacer-to-spacer distance along the first direction. The interfacial layer is on the semiconductor channel. The interfacial layer extends a length along the first direction, and the length is less than a minimum of the spacer-to-spacer distance along the first direction. The metal gate structure is over the interfacial layer.

Abstract: A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.

Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.

Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.

Abstract: Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.

Abstract: A method includes forming a mask layer above a substrate. The substrate is patterned by using the mask layer as a mask to form a trench in the substrate. An isolation structure is formed in the trench, including feeding first precursors to the substrate. A bias is applied to the substrate after feeding the first precursors. With the bias turned on, second precursors are fed to the substrate. Feeding the first precursors, applying the bias, and feeding the second precursors are repeated.

Abstract: A method includes forming a dummy gate structure over a wafer. Gate spacers are formed on either side of the dummy gate structure. The dummy gate structure is removed to form a gate trench between the gate spacers. A gate dielectric layer is formed in the gate trench. A gate electrode is formed over the gate dielectric layer. Forming the gate dielectric layer includes applying a first bias to the wafer. With the first bias turned on, first precursors are fed to the wafer. The first bias is turned off. After turning off the first bias, second precursors are fed to the wafer.

Abstract: Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.

Abstract: In this disclosure, antiferroelectric capacitors having one or more interfacial layer/antiferroelectric layer/interfacial layer stacked structures are proposed. The compressive chemical pressure of the proposed structure leads to a reduction of the hysteresis and thus a high ESD and a low energy loss. A provided antiferroelectric capacitor demonstrates a record-high ESD of 94 J/cm3 and a high efficiency of 80%, along with a high maximum power density of 5×1010 W/kg. The degradation of the energy storage performance as the film thickness increases is alleviated by the above multi-stacked structure, which presents a high ESD of 80 J/cm3 and efficiency of 82% with the thickness scaled up to 48 nm. This improvement is attributed to the enhancement of breakdown strength due to the barrier effect of interfaces on electrical treeing. Furthermore, the capacitors also exhibit an excellent endurance up to 1010 operation cycles.

Abstract: A semiconductor device includes source and a drain above a substrate and spaced apart along a first direction, and a semiconductor channel extending between the source and the drain. The semiconductor device further includes gate spacers, an interfacial layer, and a metal gate structure. The gate spacers are disposed on the semiconductor channel and spaced apart by a spacer-to-spacer distance along the first direction. The interfacial layer is on the semiconductor channel. The interfacial layer extends a length along the first direction, and the length is less than a minimum of the spacer-to-spacer distance along the first direction. The metal gate structure is over the interfacial layer.

Abstract: A multi-function equipment implements a method of fabricating a thin film. The multi-function equipment according to the invention includes a reaction chamber, a plasma source, a plasma source power generating unit, a bias electrode, an AC (Alternating Current) voltage generating unit, a DC (Direct current) bias generating unit, a metal chuck, a first precursor supply source, a second precursor supply source, a carrier gas supply source, an oxygen supply source, a nitrogen supply source, an inert gas supply source, an automatic pressure controller, and a vacuum pump.