Patents by Inventor Mika Henrik Tuomi
Mika Henrik Tuomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090096792Abstract: An efficient method for improving use of different fill modes in vector graphics and a system using the method. The filling method uses a graphics hardware that is capable of producing objects to be filled. Before the actual filling the edges of the objects must be computed. Edges are then stored into an edge buffer. The buffer may be a separate buffer block or a pointer to a memory. The edge buffer comprises only the edges of the object to be rendered. When the object is actually is rendered, rendering function is called with at least one parameter. The parameters include the fill mode with which the object is rendered to the screen.Type: ApplicationFiled: October 15, 2007Publication date: April 16, 2009Applicant: ATI Technologies ULCInventor: Mika Henrik Tuomi
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Patent number: 7489317Abstract: Antialiasing method and apparatus for video applications. A method for antialiasing a video graphic. A determination is first made as to the relative position of a desired pixel being within the polygon and proximate to the edge of the polygon. Once the relative position is known, then a determination is made as to whether it meets a first predetermined condition or a second predetermined condition. If the relative position meets the first condition, then the color of at least an adjacent pixel is blended with the color of the desired pixel in a predetermined proportion. If the relative position meets the second predetermined condition, then the color of at least an adjacent pixel is blended with the color of the desired pixel in a predetermined proportion.Type: GrantFiled: May 23, 2002Date of Patent: February 10, 2009Assignee: Bitboys Oy, A Finnish Registered CoInventors: Mika Henrik Tuomi, Sami Santeri Tammilehto, Petri Olavi Nordlund
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Publication number: 20080150951Abstract: A 3-D rendering engine with embedded memory a graphics engine. A graphics engine is disclosed that includes a rendering engine for receiving graphics primitives and converting them to pixel information for transfer to a display, The rendering engine is operable to access memory locations with multiple memory access requests for a Read or a Write operation and operable in a first address space. A plurality of memory blocks are provided, each individually accessible and all configured in a virtual address space different than said first address space. A memory mapping device is provided for mapping each of the memory requests to the virtual address space. A pipeline engine is operable to pipeline the mapped memory access requests for both Read and Write operations in accordance with a predetermined pipelining scheme. The memory access requests are received in parallel and processed asynchronously, such that access to more than one of the memory blocks can occur at substantially the same time.Type: ApplicationFiled: July 24, 2007Publication date: June 26, 2008Applicant: BITBOYS OYInventor: MIKA HENRIK TUOMI
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Patent number: 7248266Abstract: A 3-D rendering engine with embedded memory a graphics engine. A graphics engine is disclosed that includes a rendering engine for receiving graphics primitives and converting them to pixel information for transfer to a display, The rendering engine is operable to access memory locations with multiple memory access requests for a Read or a Write operation and operable in a first address space. A plurality of memory blocks are provided, each individually accessible and all configured in a virtual address space different than said first address space. A memory mapping device is provided for mapping each of the memory requests to the virtual address space. A pipeline engine is operable to pipeline the mapped memory access requests for both Read and Write operations in accordance with a predetermined pipelining scheme. The memory access requests are received in parallel and processed asynchronously, such that access to more than one of the memory blocks can occur at substantially the same time.Type: GrantFiled: February 10, 2004Date of Patent: July 24, 2007Assignee: Bitboys OyInventor: Mika Henrik Tuomi
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Patent number: 7061507Abstract: Antialiasing method and apparatus for video applications. A method for antialiasing a video graphic. First, the processor renders the pixels and, during the step of rendering, determines if an edge pixel of a polygon is being rendered. If so, a sample point is defined within each pixel and a determination made if the sample point lies within the polygon or outside of the polygon. If the sample point lies within the polygon, the color of the edge pixel is set to the color of the polygon. If the sample point lies outside of the polygon, the color of the edge pixel is set to the color of the background. The percentage of the pixel that lies in the space associated with the sampling point is then calculated. The color of the pixel is stored in a frame buffer in association with the percent value that lies in the space associated with the sample point and in association with an indication that the sample point lies within the polygon or outside of the polygon.Type: GrantFiled: November 12, 2000Date of Patent: June 13, 2006Assignee: Bitboys, Inc.Inventors: Mika Henrik Tuomi, Sami Santeri Tammilehto, Petri Olavi Nordlund
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Patent number: 6690377Abstract: A 3-D rendering engine with embedded memory a graphics engine. A graphics engine is disclosed that includes a rendering engine for receiving graphics primitives and converting them to pixel information for transfer to a display, The rendering engine is operable to access memory locations with multiple memory access requests for a Read or a Write operation and operable in a first address space. A plurality of memory blocks are provided, each individually accessible and all configured in a virtual address space different than said first address space. A memory mapping device is provided for mapping each of the memory requests to the virtual address space. A pipeline engine is operable to pipeline the mapped memory access requests for both Read and Write operations in accordance with a predetermined pipelining scheme. The memory access requests are received in parallel and processed asynchronously, such that access to more than one of the memory blocks can occur at substantially the same time.Type: GrantFiled: November 12, 2001Date of Patent: February 10, 2004Assignee: Bitboys OyInventor: Mika Henrik Tuomi
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Publication number: 20030095134Abstract: Antialiasing method and apparatus for video applications. A method for antialiasing a video graphic. A determination is first made as to the relative position of a desired pixel being within the polygon and proximate to the edge of the polygon. Once the relative position is known, then a determination is made as to whether it meets a first predetermined condition or a second predetermined condition. If the relative position meets the first condition, then the color of at least an adjacent pixel is blended with the color of the desired pixel in a predetermined proportion. If the relative position meets the second predetermined condition, then the color of at least an adjacent pixel is blended with the color of the desired pixel in a predetermined proportion.Type: ApplicationFiled: May 23, 2002Publication date: May 22, 2003Inventors: Mika Henrik Tuomi, Sami Santeri Tammilehto, Petri Olavi Nordlund
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Publication number: 20030001852Abstract: A 3-D rendering engine with embedded memory a graphics engine. A graphics engine is disclosed that includes a rendering engine for receiving graphics primitives and converting them to pixel information for transfer to a display, The rendering engine is operable to access memory locations with multiple memory access requests for a Read or a Write operation and operable in a first address space. A plurality of memory blocks are provided, each individually accessible and all configured in a virtual address space different than said first address space. A memory mapping device is provided for mapping each of the memory requests to the virtual address space. A pipeline engine is operable to pipeline the mapped memory access requests for both Read and Write operations in accordance with a predetermined pipelining scheme. The memory access requests are received in parallel and processed asynchronously, such that access to more than one of the memory blocks can occur at substantially the same time.Type: ApplicationFiled: November 12, 2001Publication date: January 2, 2003Inventor: Mika Henrik Tuomi