Patents by Inventor Mika Kiritani

Mika Kiritani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160276312
    Abstract: A semiconductor device includes a wiring substrate, a first semiconductor chip provided on the wiring substrate, a supporting member provided on the wiring substrate in a region which does not overlap with the first semiconductor chip in a plan view when viewed from a direction perpendicular to the wiring substrate, a resin member provided on the first semiconductor chip, and a second semiconductor chip provided on the supporting member and the resin member. A method for manufacturing a semiconductor device includes providing a first semiconductor chip in a first region on a wiring substrate, providing a supporting member in a second region on the wiring substrate, providing a resin member in at least a portion on the first semiconductor chip, and providing a second semiconductor chip on the supporting member and the resin member.
    Type: Application
    Filed: March 4, 2016
    Publication date: September 22, 2016
    Inventors: Shinya SHIMIZU, Mika KIRITANI, Ken MURAMATSU
  • Publication number: 20120235282
    Abstract: According to one embodiment, a semiconductor device manufacturing method is disclosed. The method comprises (a) forming cut grooves in a front surface of a semiconductor wafer on which semiconductor elements are formed to partition the front surface into a plurality of regions, (b) disposing partly a resin in the cut grooves, (c) adhering a protection tape on the front surface of the semiconductor wafer, (d) thinning the semiconductor wafer by grinding a rear surface of the semiconductor wafer to reach the cut grooves, (e) forming an adhesive agent layer on the rear surface of the semiconductor wafer, and (f) dividing the semiconductor wafer into a plurality of semiconductor chips by cutting the adhesive agent layer together with the disposed resin along the cut grooves.
    Type: Application
    Filed: February 14, 2012
    Publication date: September 20, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira TOMONO, Tetsuya KUROSAWA, Tsutomu FUJITA, Mika KIRITANI, Shinya TAKYU
  • Patent number: 7833836
    Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: November 16, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Takyu, Kazuhiro Iizuka, Mika Kiritani
  • Patent number: 7608911
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: October 27, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
  • Publication number: 20090111218
    Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.
    Type: Application
    Filed: December 31, 2008
    Publication date: April 30, 2009
    Inventors: Shinya TAKYU, Kazuhiro Iizuka, Mika Kiritani
  • Patent number: 7482695
    Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: January 27, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Takyu, Kazuhiro Iizuka, Mika Kiritani
  • Publication number: 20080265443
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.
    Type: Application
    Filed: June 24, 2008
    Publication date: October 30, 2008
    Applicant: Kabushiki Kaisha Toshiba,
    Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
  • Patent number: 7405159
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: July 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
  • Publication number: 20070262445
    Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.
    Type: Application
    Filed: July 13, 2007
    Publication date: November 15, 2007
    Inventors: Shinya Takyu, Kazuhiro Iizuka, Mika Kiritani
  • Patent number: 7285864
    Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: October 23, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Takyu, Kazuhiro Iizuka, Mika Kiritani
  • Publication number: 20070196956
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.
    Type: Application
    Filed: March 1, 2007
    Publication date: August 23, 2007
    Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
  • Patent number: 7202563
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: April 10, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
  • Publication number: 20050212145
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.
    Type: Application
    Filed: March 25, 2005
    Publication date: September 29, 2005
    Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
  • Publication number: 20050179127
    Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.
    Type: Application
    Filed: July 15, 2004
    Publication date: August 18, 2005
    Inventors: Shinya Takyu, Kazuhiro Iizuka, Mika Kiritani
  • Publication number: 20050026326
    Abstract: A manufacturing method of a semiconductor device to electrically connect a semiconductor chip and a wiring board via a first bump electrode, at least one of the semiconductor chip and the wiring board having a second bump electrode or a connection electrode, the method includes: collectively performing flip chip bonding of the semiconductor chip to the wiring board and resin sealing processing between the semiconductor chip and the wiring board; wherein the collective processing includes controlling viscosity of a sealing resin with ultrasonic vibration so that the first bump electrode penetrates the sealing resin; and using the ultrasonic vibration to electrically connect the first bump electrode to the second bump electrode when at least one of the semiconductor chip and the wiring board has the second bump electrode, or using the ultrasonic vibration to electrically connect the first bump electrode to the connection electrode when at least one of the semiconductor chip and the wiring board has the connecti
    Type: Application
    Filed: May 12, 2004
    Publication date: February 3, 2005
    Inventors: Mika Kiritani, Shinya Takyu, Kazuhiro Iizuka
  • Patent number: 6787093
    Abstract: A resin tape substrate with a semiconductor chip mounted thereon is put to an attachment area surface of a cavity bottom surface, and a plurality of suction holes connected to a suction system are disposed in the attachment area surface, wherein the attachment area surface of the cavity is formed in a semiconductor resin mold, so that the molten resin given into the cavity does not flow into the back surface of the resin tape substrate which is sucked on the attachment area surface in the mold.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: September 7, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mika Kiritani
  • Patent number: 6777313
    Abstract: Bumps electrically connected to elements are formed on the main surface of a wafer on which the elements are formed and grooves with depths which do not reach the back surface of the wafer are formed in the wafer on the main surface side thereof along dicing lines or chip dividing lines of the wafer. The bump forming surface of the wafer is coated with a seal member and a back side grinding process for the wafer is performed to make the wafer thin, and at the same time, divide the wafer into individual chips. One of the chips which are discretely divided by performing the back side grinding process is picked up, the bumps of the picked-up chip are bonded and mounted to and on a base board, and at the same time, the seal member is melted for sealing.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: August 17, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Takyu, Mika Kiritani, Tetsuya Kurosawa, Terunari Takano
  • Publication number: 20030017663
    Abstract: Bumps electrically connected to elements are formed on the main surface of a wafer on which the elements are formed and grooves with depths which do not reach the back surface of the wafer are formed in the wafer on the main surface side thereof along dicing lines or chip dividing lines of the wafer. The bump forming surface of the wafer is coated with a seal member and a back side grinding process for the wafer is performed to make the wafer thin, and at the same time, divide the wafer into individual chips. One of the chips which are discretely divided by performing the back side grinding process is picked up, the bumps of the picked-up chip are bonded and mounted to and on a base board, and at the same time, the seal member is melted for sealing.
    Type: Application
    Filed: July 3, 2002
    Publication date: January 23, 2003
    Inventors: Shinya Takyu, Mika Kiritani, Tetsuya Kurosawa, Terunari Takano
  • Publication number: 20020020940
    Abstract: A resin tape substrate with a semiconductor chip mounted thereon is put to an attachment area surface of a cavity bottom surface, and a plurality of suction holes connected to a suction system are disposed in the attachment area surface, wherein the attachment area surface of the cavity is formed in a semiconductor resin mold, so that the molten resin given into the cavity does not flow into the back surface of the resin tape substrate which is sucked on the attachment area surface in the mold.
    Type: Application
    Filed: June 25, 2001
    Publication date: February 21, 2002
    Inventor: Mika Kiritani