Abstract: Suitably arranged circuits located on a die surface of respective multiple dies are operatively connected via a physical link, which is configured for full-duplex operation. Data information content is transferred between the operatively connected suitably arranged circuits via the full-duplex physical link which is configured as a fragmented data interconnected (FDI) physical link allowing peer-to-peer operation and pipelining. The data information content is carried in data fragments by a self-contained data packet structure. In one embodiment a device comprises a first suitably arranged and configured circuit located on a die surface, a second suitably arranged and configured circuit located on a die surface and a full-duplex physical link arranged and configured for operatively connecting the first circuit located on the die surface to the second circuit located on the die surface for transferring data information content between the first circuit and the second circuit.

Abstract: A device comprises an integrated circuit having first and second domains, the first domain having a first clock boundary module; and the second domain having a second clock boundary module. The first clock boundary module comprises: a buffer, for storing data for transfer to the second domain; and a first controller operable to send a first control signal to the second clock boundary module via a first synchronizer, the first control signal indicating the presence of a packet of data in a first storage location of the buffer. One of the first and second clock boundary modules comprises a multiplexer having an input connected to an output of the buffer and an output connected to circuitry forming part of the second domain.

Abstract: A device comprises an integrated circuit having first and second domains, the first domain having a first clock boundary module; and the second domain having a second clock boundary module. The first clock boundary module comprises: a buffer, for storing data for transfer to the second domain; and a first controller operable to send a first control signal to the second clock boundary module via a first synchroniser, the first control signal indicating the presence of a packet of data in a first storage location of the buffer. One of the first and second clock boundary modules comprises a multiplexer having an input connected to an output of the buffer and an output connected to circuitry forming part of the second domain.

Abstract: Suitably arranged circuits located on a die surface are operatively connected via a shared link which is configured for carrying data information content between the suitably arranged circuits. A suitably arranged and configured system status signal is transferred between a first of the suitably arranged circuits and a second of the suitably arranged circuits via the shared link for mirroring a system status of the first of the suitably arranged circuits in the second of the suitably arranged circuits. In one embodiment, the system status signal is arranged and configured as part of the data information content data packet structure carried between the suitably configured circuits. The system status signal comprises a collection of bit signals arranged and configured for indicating a status of a corresponding on-chip-interconnect access in the first of the suitably arranged circuits.

Abstract: Suitably arranged circuits located on a die surface of respective multiple dies are operatively connected via a physical link, which is configured for full-duplex operation. Data information content is transferred between the operatively connected suitably arranged circuits via the full-duplex physical link which is configured as a fragmented data interconnected (FDI) physical link allowing peer-to-peer operation and pipelining. The data information content is carried in data fragments by a self-contained data packet structure.

Abstract: A method and apparatus are provided to arbitrate multiple master requests to a shared resource, featuring a step of combining two different ways to arbitrate the multiple master requests to the shared resource in an operation independent manner. The two different ways may include a priority arbitration technique and a round robin arbitration technique. The priority arbitration technique may include a time division priority selection technique. The shared resource may include a set of one or more peripherals and/or memories. The step may be implemented in an application specific integrated circuit (ASIC) or other suitable application environment, which includes video, graphic, cellular or other suitable functionality.