Patents by Inventor Mika Nakamura
Mika Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11918568Abstract: The present invention relates to a novel fused ring compound having urea structure that exhibits excellent NAMPT activating effect, and a method using the same for treating/preventing metabolic disorder, cardiovascular and kidney disease, mitochondrial disease, neurodegenerative disease, ocular disease, and muscle wasting disorder. The present invention provides a compound represented by following formula (I) or a pharmacologically acceptable salt: Formula (I) wherein A, B, R, R2 and R3 represent the same meanings as in the claims.Type: GrantFiled: July 3, 2019Date of Patent: March 5, 2024Assignee: SANFORD BURNHAM PREBYS MEDICAL DISCOVERY INSTITUTEInventors: Tsuyoshi Nakamura, Mayuko Akiu, Takashi Tsuji, Jun Tanaka, Koji Terayama, Mika Yokoyama, Anthony B. Pinkerton, Edward Hampton Sessions
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Patent number: 9734758Abstract: A display device includes light-emitting pixels, a voltage source, power supply lines for supplying drive voltage from the voltage source to each light-emitting pixel, a voltage drop amount estimating unit which estimates an amount of voltage drop between the voltage source and each light-emitting pixel, using video data indicating light emission luminance of each light-emitting pixel, a first storage unit which holds correction information indicating light emission characteristics obtained when a driving transistor in the light-emitting pixel operates both in linear and saturated regions, a second storage unit which holds reference characteristic information indicating light emission characteristics obtained when the driving transistor operates in the saturated region, and a luminance signal correcting unit which generates the luminance signal by correcting a reference level of the luminance signal associated with the light emission luminance, based on the estimated amount of voltage drop and the correctionType: GrantFiled: October 15, 2014Date of Patent: August 15, 2017Assignee: JOLED INC.Inventors: Yuki Imai, Tomoyuki Maeda, Mika Nakamura
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Publication number: 20160232842Abstract: A display device includes light-emitting pixels, a voltage source, power supply lines for supplying drive voltage from the voltage source to each light-emitting pixel, a voltage drop amount estimating unit which estimates an amount of voltage drop between the voltage source and each light-emitting pixel, using video data indicating light emission luminance of each light-emitting pixel, a first storage unit which holds correction information indicating light emission characteristics obtained when a driving transistor in the light-emitting pixel operates both in linear and saturated regions, a second storage unit which holds reference characteristic information indicating light emission characteristics obtained when the driving transistor operates in the saturated region, and a luminance signal correcting unit which generates the luminance signal by correcting a reference level of the luminance signal associated with the light emission luminance, based on the estimated amount of voltage drop and the correctionType: ApplicationFiled: October 15, 2014Publication date: August 11, 2016Applicant: JOLED INC.Inventors: Yuki IMAI, Tomoyuki MAEDA, Mika NAKAMURA
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Patent number: 9024920Abstract: N drivers convert n digital values into n voltages. N amplifiers amplify the n voltages, thereby generate n drive voltages. An amplifier voltage supply supplies an amplifier voltage for driving the n amplifiers. An amplifier voltage controller detects a maximum digital value among a plurality of digital values, and sets the amplifier voltage to a voltage value dependent on the maximum digital value.Type: GrantFiled: July 19, 2011Date of Patent: May 5, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Hiroshi Kojima, Kazuyoshi Nishi, Takashi Koizumi, Mika Nakamura, Yosuke Izawa
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Patent number: 8687024Abstract: An active matrix display apparatus comprises plural gate lines and plural source lines that are arranged such that the plural gate lines respectively intersect the plural source lines and light-emitting element circuits, which are provided to respectively correspond to intersections at which the plural gate lines intersect the plural source line. Additionally, each of the light-emitting element circuits includes a light-emitting element for emitting light according to a current supplied thereto, a drive transistor for controlling a current supplied to the light-emitting element, and a control transistor for controlling writing of an image signal to the drive transistor. Furthermore, the drive transistor has a body terminal and is configured to correct luminance of the light-emitting element using a voltage applied to the body terminal.Type: GrantFiled: March 8, 2010Date of Patent: April 1, 2014Assignee: Panasonic CorporationInventors: Arinobu Kanegae, Shinya Ono, Mika Nakamura
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Patent number: 8552940Abstract: A display device includes luminescence pixels that each include a driving transistor, a luminescence element, and a switching transistor that switches between conduction and non-conduction between a data line and an anode or a cathode of the luminescence element. A data driving circuit supplies a signal voltage to the data line, and a bias supplying circuit supplies a predetermined bias voltage to the data line. A controller applies the predetermined bias voltage to the anode or the cathode of the luminescence element by causing a non-conduction state between the data line and the data driving circuit, causing a conduction state between the data line and the bias supplying circuit, and switching the switching transistor ON within a period in which a signal current does not flow to the luminescence element.Type: GrantFiled: June 14, 2012Date of Patent: October 8, 2013Assignee: Panasonic CorporationInventors: Mika Nakamura, Kenichi Masumoto
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Patent number: 8368620Abstract: An organic EL display panel includes: a P-type drive transistor having a gate connected to a capacitor and a drain connected to an organic EL element; an N-type drive transistor having a gate connected to the capacitor and a source connected to the organic EL element; a first power source line for applying a first voltage to the P-type drive transistor; a second power source line for applying, to the N-type drive transistor, a second voltage higher than the first voltage. The P-type drive transistor has characteristics such that a first gate voltage value corresponding to a predetermined current value in current-voltage characteristics of the organic EL element is a minimum voltage of the data voltage, and the N-type drive transistor has characteristics such that a second gate voltage value corresponding to the predetermined current value is greater than a third gate voltage value corresponding to a minimum current value of the organic EL element.Type: GrantFiled: January 25, 2012Date of Patent: February 5, 2013Assignee: Panasonic CorporationInventors: Yosuke Izawa, Mika Nakamura
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Patent number: 8339338Abstract: A display device includes a display that includes display elements arranged in lines of a matrix. Each display element is configured to emit light based on a video signal that is received by the display. A proportion determiner is configured to determine, for each line, a proportion of a single frame period during which each display element of a corresponding line is not to emit the light. A signal converter is configured to convert an amplitude of the video signal for each line according to the proportion determined for each line. A signal output is configured to output the video signal converted by the signal converter to the display as a converted video signal. A scanner is configured to output a scanning signal to the display for each line for inputting the converted video signal to the display elements of each line based on the proportion determined for each line.Type: GrantFiled: June 8, 2011Date of Patent: December 25, 2012Assignee: Panasonic CorporationInventor: Mika Nakamura
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Publication number: 20120249612Abstract: A display device includes luminescence pixels that each include a driving transistor, a luminescence element, and a switching transistor that switches between conduction and non-conduction between a data line and an anode or a cathode of the luminescence element. A data driving circuit supplies a signal voltage to the data line, and a bias supplying circuit supplies a predetermined bias voltage to the data line. A controller applies the predetermined bias voltage to the anode or the cathode of the luminescence element by causing a non-conduction state between the data line and the data driving circuit, causing a conduction state between the data line and the bias supplying circuit, and switching the switching transistor ON within a period in which a signal current does not flow to the luminescence element.Type: ApplicationFiled: June 14, 2012Publication date: October 4, 2012Applicant: PANASONIC CORPORATIONInventors: Mika NAKAMURA, Kenichi MASUMOTO
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Publication number: 20120188221Abstract: An organic EL display panel includes a P-type drive transistor having a gate connected to a capacitor and a drain connected to an organic EL element, an N-type drive transistor having a gate connected to the capacitor and a source connected to the element, a power line for applying a voltage to the P-type drive transistor, another power line for applying a higher voltage to the N-type drive transistor. The transistors have characteristics whereby, a first gate voltage value corresponding to a predetermined current value in current-voltage characteristics of the element is a minimum voltage of the data voltage, and a second gate voltage value corresponding to the predetermined current value is greater than a third gate voltage value corresponding to a minimum current value of the element.Type: ApplicationFiled: January 25, 2012Publication date: July 26, 2012Applicant: Panasonic CorporationInventors: Yosuke IZAWA, Mika NAKAMURA
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Patent number: 8223094Abstract: Display devices and methods capable of reversing brightness deterioration in electroluminescence elements while maintaining display quality, with simple pixel circuits and no manufacturing yield reduction, are provided. A display device includes luminescence pixels that each include a driving transistor, a luminescence element, and a switching transistor which switches between conduction and non-conduction states between a data line and the luminescence element. A data driving circuit supplies a signal voltage to the data line and a bias supplying circuit supplies a specified bias voltage to the data line. A control unit applies the specified bias voltage to an anode or cathode of the luminescence element by causing conduction between the data line and the data driving circuit, causing non-conduction between the data line and the bias supplying circuit, and turning the switching transistor ON, all within a period in which a signal current does not flow to the luminescence element.Type: GrantFiled: February 26, 2010Date of Patent: July 17, 2012Assignee: Panasonic CorporationInventors: Mika Nakamura, Kenichi Masumoto
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Patent number: 8179403Abstract: When composite image data including parts that were respectively in different data formats before combining, is conventionally edited, the whole composite image data is edited by using a same algorithm. The algorithm may not be an optimum algorithm for a certain part of the composite image data. In an improved structure, the format conversion unit 142 converts the format of the combining target image data, attaches, to each piece of pixel data, a flag indicating the data format before the conversion, and outputs the pixel data with the flag. The combining engine 143 combines together the image data output from the format conversion unit 142.Type: GrantFiled: September 11, 2007Date of Patent: May 15, 2012Assignee: Panasonic CorporationInventor: Mika Nakamura
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Publication number: 20110273425Abstract: N drivers convert n digital values into n voltages. N amplifiers amplify the n voltages, thereby generate n drive voltages. An amplifier voltage supply supplies an amplifier voltage for driving the n amplifiers. An amplifier voltage controller detects a maximum digital value among a plurality of digital values, and sets the amplifier voltage to a voltage value dependent on the maximum digital value.Type: ApplicationFiled: July 19, 2011Publication date: November 10, 2011Applicant: Panasonic CorporationInventors: Hiroshi Kojima, Kazuyoshi Nishi, Takashi Koizumi, Mika Nakamura, Yosuke Izawa
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Publication number: 20110234911Abstract: A display device includes a display that includes display elements arranged in lines of a matrix. Each display element is configured to emit light based on a video signal that is received by the display. A proportion determiner is configured to determine, for each line, a proportion of a single frame period during which each display element of a corresponding line is not to emit the light. A signal converter is configured to convert an amplitude of the video signal for each line according to the proportion determined for each line. A signal output is configured to output the video signal converted by the signal converter to the display as a converted video signal. A scanner is configured to output a scanning signal to the display for each line for inputting the converted video signal to the display elements of each line based on the proportion determined for each line.Type: ApplicationFiled: June 8, 2011Publication date: September 29, 2011Applicant: PANASONIC CORPORATIONInventor: Mika NAKAMURA
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Patent number: 7936350Abstract: In a display control circuit for controlling a display of a display device, data which is stored in a memory is inputted to a FIFO circuit by a DMA controller, and the FIFO circuit transmits the stored data to the display device at a rising edge of an inputted clock PCLK. A clock mask circuit transmits the inputted clock PCLK to the display device as a display clock PCLK? while the FIFO circuit is not underflow. On the other hand, the clock mask circuit masks the inputted clock PCLK while the FIFO circuit is underflow, and transmits the display clock PCLK? whose level is kept high to the display device. As a result, a display position of display data does not shift even if underflow occurs in the FIFO circuit.Type: GrantFiled: March 16, 2006Date of Patent: May 3, 2011Assignee: Panasonic CorporationInventors: Mika Nakamura, Hiroki Taoka
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Publication number: 20100220118Abstract: An active matrix display apparatus of the present invention comprises plural gate lines and plural source lines which are arranged such that the plural gate lines respectively intersect the plural source lines and light-emitting element circuits which are provided to respectively correspond to intersections at which the plural gate lines intersect the plural source line, respectively; wherein each of the light-emitting element circuits includes a light-emitting element for emitting light according to a current supplied thereto; a drive transistor for controlling a current supplied to the light-emitting element; and a control transistor for controlling an ON/OFF operation of the drive transistor; wherein the drive transistor has a body terminal and is configured to correct luminance of the light-emitting element using a voltage applied to the body terminal.Type: ApplicationFiled: March 8, 2010Publication date: September 2, 2010Applicant: PANASONIC CORPORATIONInventors: Arinobu KANEGAE, Shinya ONO, Mika NAKAMURA
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Publication number: 20100149140Abstract: Display devices and methods capable of reversing brightness deterioration in electroluminescence elements while maintaining display quality, with simple pixel circuits and no manufacturing yield reduction, are provided. A display device includes luminescence pixels that each include a driving transistor, a luminescence element, and a switching transistor which switches between conduction and non-conduction states between a data line and the luminescence element. A data driving circuit supplies a signal voltage to the data line and a bias supplying circuit supplies a specified bias voltage to the data line. A control unit applies the specified bias voltage to an anode or cathode of the luminescence element by causing conduction between the data line and the data driving circuit, causing non-conduction between the data line and the bias supplying circuit, and turning the switching transistor ON, all within a period in which a signal current does not flow to the luminescence element.Type: ApplicationFiled: February 26, 2010Publication date: June 17, 2010Applicant: PANASONIC CORPORATIONInventors: Mika NAKAMURA, Kenichi MASUMOTO
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Publication number: 20100079492Abstract: When composite image data including parts that were respectively in different data formats before combining, is conventionally edited, the whole composite image data is edited by using a same algorithm. The algorithm may not be an optimum algorithm for a certain part of the composite image data. In an improved structure, the format conversion unit 142 converts the format of the combining target image data, attaches, to each piece of pixel data, a flag indicating the data format before the conversion, and outputs the pixel data with the flag. The combining engine 143 combines together the image data output from the format conversion unit 142.Type: ApplicationFiled: September 11, 2007Publication date: April 1, 2010Inventor: Mika Nakamura
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Publication number: 20090109207Abstract: In a display control circuit 11 for controlling a display of a display device 12, data which is stored in a memory 13 is inputted to a FIFO circuit 111 by a DMA controller 14, and the FIFO circuit 111 transmits the stored data to the display device 12 at a rising edge of an inputted clock PCLK. A clock mask circuit 112 transmits the inputted clock PCLK to the display device 12 as a display clock PCLK? while the FIFO circuit 111 is not underflow. On the other hand, the clock mask circuit 112 masks the inputted clock PCLK while the FIFO circuit 111 is underflow, and transmits the display clock PCLK? whose level is kept high to the display device 12. As a result, a display position of display data does not shift even if underflow occurs in the FIFO circuit 111.Type: ApplicationFiled: March 16, 2006Publication date: April 30, 2009Inventors: Mika Nakamura, Hiroki Taoka
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Patent number: 7515311Abstract: An image synthesis apparatus stores a synthesis order in which input images are to be synthesized with each other, and first and second synthesis numbers respectively designating how many of the input images are to be synthesized to generate first and second output images. The image synthesis apparatus synthesizes the plurality of input images with each other sequentially in accordance with the synthesis order, and stores a resultant synthesized image. When the stored synthesized image is the first output image, generated by synthesizing the first synthesis number of input images in accordance with the synthesis order, the first output image is output to an external destination. When the stored synthesized image is the second output image, generated by synthesizing the first output image with the remaining input images in the synthesis order, the stored second output image is output to the external destination.Type: GrantFiled: October 11, 2005Date of Patent: April 7, 2009Assignee: Panasonic CorporationInventor: Mika Nakamura