Abstract: Extension regions 7 are formed through implantation using offset sidewalls 6a of a footing profile as a mask, and sidewalls 9 are formed on the offset sidewalls 6a so that source and drain regions 10 are formed into the sidewall through implantation, so that the extension regions 7 are made separated away from both edges of the gate, contributing to enlargement in an effective gate length, and dealing with the narrowed gate pitch, without increasing the number of processes.

Abstract: Extension regions 7 are formed through implantation using offset sidewalls 6a of a footing profile as a mask, and sidewalls 9 are formed on the offset sidewalls 6a so that source and drain regions 10 are formed into the sidewall through implantation, so that the extension regions 7 are made separated away from both edges of the gate, contributing to enlargement in an effective gate length, and dealing with the narrowed gate pitch, without increasing the number of processes.

Abstract: A semiconductor device is provided, which includes a circuit including a first MOS transistor having a gate connected to a first signal line, a second MOS transistor having a gate connected to a second signal line, and the circuit outputting an output signal according to a difference in potential between the first signal line and the second signal line, wherein channel regions of the first and second MOS transistors include no maximum impurity concentration at an area, which is shallower than a depth indicating a maximum concentration of one conduction type impurity that forms source and drain regions of the MOS transistors.

Abstract: A semiconductor device is provided, which includes a circuit including a first MOS transistor having a gate connected to a first signal line, a second MOS transistor having a gate connected to a second signal line, and the circuit outputting an output signal according to a difference in potential between the first signal line and the second signal line, wherein channel regions of the first and second MOS transistors include no maximum impurity concentration at an area, which is shallower than a depth indicating a maximum concentration of one conduction type impurity that forms source and drain regions of the MOS transistors.

Abstract: A semiconductor device has first and second conductive type transistors on a substrate. First conductive type transistor includes: a first lower gate electrode portion on the substrate, including silicon including first impurity ions; a first intervening layer on the first lower gate electrode portion, including silicon including oxygen and/or nitrogen; and a first upper gate electrode portion on the first intervening layer, the first upper gate electrode portion including silicon including the first impurity ions.

Abstract: Extension regions 7 are formed through implantation using offset sidewalls 6a of a footing profile as a mask, and sidewalls 9 are formed on the offset sidewalls 6a so that source and drain regions 10 are formed into the sidewall through implantation, so that the extension regions 7 are made separated away from both edges of the gate, contributing to enlargement in an effective gate length, and dealing with the narrowed gate pitch, without increasing the number of processes.

Abstract: In the semiconductor memory of the present invention, the impurity concentration of the high-doped region in the drain region is lower than that of the high-doped region in the source region. The drain region having a lower impurity concentration suppresses the GIDL leakage. The source region having a higher impurity concentration suppresses the leakage of stored charge to between the body and the source region. As a result, the semiconductor memory is enabled to have a memory cell with excellent data holding characteristic.