Patents by Inventor Mika Shiiki

Mika Shiiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050106830
    Abstract: There are provided a bleeder resistance circuit which has an accurate voltage dividing ratio, a small temperature coefficient of a resistance value, and high precision, and a semiconductor device using such a bleeder resistance circuit, which has high precision and a small temperature coefficient, such as a voltage detector or a voltage regulator. In the bleeder resistance circuit using a thin film resistor, conductors located over and under the thin film resistor are made to have substantially the same potential as the thin film resistor. Further, when polysilicon is used for the thin film resistor, the film thickness of the polysilicon thin film resistor is thinned, and an impurity introduced into the polysilicon thin film resistor is made to be a P-type. Thus, a variation in a resistance value is suppressed, and a temperature dependency of the resistance value is made small.
    Type: Application
    Filed: December 3, 2004
    Publication date: May 19, 2005
    Inventors: Mika Shiiki, Hiroaki Takasu
  • Patent number: 6844599
    Abstract: A semiconductor device has thin film resistors connected in series to form a bleeder resistance circuit. Each of the thin film resistors is made of a polysilicon film doped with B or BF2 P-type impurities and has two end portions each having a high impurity concentration region. A first insulating film overlies the thin film resistors. First conductors are connected to the ends of the thin film resistors for connecting the thin film resistors in series. The semiconductor device has second conductors each connected to a respective one of the first conductors and overlying a respective one of the thin film resistors through the first insulating film.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: January 18, 2005
    Assignee: Seiko Instruments Inc.
    Inventors: Mika Shiiki, Hiroaki Takasu
  • Patent number: 6777754
    Abstract: A semiconductor device a bleeder resistance circuit having conductors, an insulating film disposed on the conductors, and thin film resistors each overlying a respective one of the conductors with the insulating film disposed therebetween. Each of the thin film resistors contains p-type impurities and has a thickness in the range of 10 to 2000 angstroms. Each of the conductors is electrically connected to and has the same electric potential as a respective one of the thin film resistors.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: August 17, 2004
    Assignee: Seiko Instruments Inc.
    Inventor: Mika Shiiki
  • Patent number: 6727556
    Abstract: A semiconductor device has a semiconductor element formed on a semiconductor substrate and a first insulating film having contact holes. The semiconductor element has a gate electrode, a source region and a drain region. The semiconductor element also has metal wirings each for connecting a respective one of the contact holes to the gate electrode, the source region and the drain region of the semiconductor element. A second insulating film is formed on the first insulating film and the metal wirings. The second insulating film has a chemical-mechanical polished portion defining a flattened upper surface of the second insulating film. Resistors are formed on and are disposed directly in contact with the flattened upper surface of the second insulating film and are connected in series to form a bleeder resistor circuit or a ladder circuit.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: April 27, 2004
    Assignee: Seiko Instruments Inc.
    Inventors: Mika Shiiki, Minoru Sudou
  • Publication number: 20030160285
    Abstract: To provide a high precision bleeder resistance circuit having an accurate divided voltage ratio and a small temperature coefficient of a resistance value, and to provide semiconductor devices having high precision and a small temperature coefficient by using the bleeder resistance circuit. For example, semiconductor devices such as a voltage detector and a voltage regulator are provided. Electric potentials of a conductor on thin film resistors and of a conductor under the thin film resistors are made nearly equal to that of each thin film resistor in a bleeder resistance circuit using the thin film resistors. In addition, if polysilicon is used in the thin film resistors, dispersion in the resistance values is suppressed, and temperature dependence of the resistance values is eliminated, by making a film thickness of the polysilicon thin film resistors thin, and making an impurity introduced into the polysilicon thin film resistors p-type.
    Type: Application
    Filed: January 9, 2003
    Publication date: August 28, 2003
    Inventor: Mika Shiiki
  • Patent number: 6534827
    Abstract: Ion implantation is conducted using contact holes of a MOS transistor as.a mask to form high concentration diffusion regions, whereby a MOS transistor having a medium withstand voltage structure is provided, in which a high drain withstand voltage, a small capacitance between a source/drain region and a gate electrode, and a high junction withstand voltage between a source/drain region and a channel stop region under a field oxide film are obtained, and the drain withstand voltage can be controlled. Low impurity concentration source and drain regions of a second conductivity type are formed in a semiconductor substrate surrounded by a field oxide film and a gate electrode. An interlayer insulating film is formed thereover for electrically insulating a gate electrode and the source and drain regions. A wiring layer is formed on the interlayer insulating film.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: March 18, 2003
    Assignee: Seiko Instruments Inc.
    Inventors: Mika Shiiki, Jun Osanai
  • Publication number: 20020047183
    Abstract: There are provided a bleeder resistance circuit which has an accurate voltage dividing ratio, a small temperature coefficient of a resistance value, and high precision, and a semiconductor device using such a bleeder resistance circuit, which has high precision and a small temperature coefficient, such as a voltage detector or a voltage regulator. In the bleeder resistance circuit using a thin film resistor, conductors located over and under the thin film resistor are made to have substantially the same potential as the thin film resistor. Further, when polysilicon is used for the thin film resistor, the film thickness of the polysilicon thin film resistor is thinned, and an impurity introduced into the polysilicon thin film resistor is made to be a P-type. Thus, a variation in a resistance value is suppressed, and a temperature dependency of the resistance value is made small.
    Type: Application
    Filed: July 27, 2001
    Publication date: April 25, 2002
    Inventors: Mika Shiiki, Hiroaki Takasu
  • Patent number: 6376896
    Abstract: A semiconductor device comprises a ladder resistor circuit formed of a polycrystal silicon film having a thickness of 500-1500 Å and a sheet resistance of 1-5 k&OHgr;/. The polycrystal silicon film is doped only with p-type impurities.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: April 23, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Mika Shiiki, Jun Osanai
  • Publication number: 20020020879
    Abstract: To provide a miniaturized and integrated semiconductor device with a resistor structuring a ladder circuit or the like. An insulating film is formed on a semiconductor substrate formed with a semiconductor element, and leveling of the top surface is performed by CMP or the like. Then, a resistor is formed not only on a field region through the leveled insulating film, but also on an active region where the semiconductor element is formed. Further, an insulating film is further formed on the resistor, and electrodes are formed in the resistor through contact holes.
    Type: Application
    Filed: July 26, 2001
    Publication date: February 21, 2002
    Inventors: Mika Shiiki, Minoru Sudou
  • Publication number: 20010040259
    Abstract: An objective of the present invention is to realize a comparator which uses MOS transistors and has a reduced offset voltage and occupies a small surface area. This is characterized in that an impurity is introduced into a channel region of a MOS transistor, the mobility of a load side MOS transistor is made smaller than the mobility of a differential side MOS transistor, and the mutual conductance of the load side MOS transistor is made smaller than the mutual conductance of the differential side MOS transistor.
    Type: Application
    Filed: April 12, 2000
    Publication date: November 15, 2001
    Inventors: Mika Shiiki, Kenji Kitamura
  • Publication number: 20010030345
    Abstract: Ion implantation is conducted using contact holes of a MOS transistor as a mask to form high concentration diffusion regions, whereby a MOS transistor having a medium withstand voltage structure is provided, in which a high drain withstand voltage, a small capacitance between a source/drain region and a gate electrode, and a high junction withstand voltage between a source/drain region and a channel stop region under a field oxide film are obtained, and the drain withstand voltage can be controlled.
    Type: Application
    Filed: March 14, 2001
    Publication date: October 18, 2001
    Inventors: Mika Shiiki, Jun Osanai
  • Patent number: 6184558
    Abstract: An object of the invention is to reduce an offset voltage to realize a small occupying area in a comparator using MOS type transistors. The invention is characterized in that impurities are introduced into channel areas of MOS type transistors, and mobility of the MOS type transistor on a load side is smaller than mobility of the MOS type transistor on a differential side, and a mutual conductance gm of the MOS type transistor on the load side is smaller than a mutual conductance gm of the MOS type transistor on the differential side.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: February 6, 2001
    Assignee: Seiko Instruments Inc.
    Inventors: Kenji Kitamura, Mika Shiiki, Jun Osanai