Abstract: Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data conversions. In these CDACs, matching of capacitive values is important, and for conventional high resolution SAR ADCs, complex trimming or calibration procedures can be too costly. Here, however, a SAR ADC is provided that performs error correction so as to reduce the overall cost compared to conventional SAR ADCs.

Abstract: Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data conversions. In these CDACs, matching of capacitive values is important, and for conventional high resolution SAR ADCs, complex trimming or calibration procedures can be too costly. Here, however, a SAR ADC is provided that performs error correction so as to reduce the overall cost compared to conventional SAR ADCs.

Abstract: A resolver arrangement that is inexpensive and yet offers high resolution and high noise rejection includes a carrier signal generator and two processing channels each of which has an analog input connected a different one of the stator coils and a channel output. Each of the processing channels includes a sigma-delta modulator with an output that supplies a bit-stream representative of an analog input signal received from a respective stator coil. Each channel also includes a first digital filter that receives the bit-stream from the sigma-delta modulator and converts the bit-stream to intermediate digital data-words. In addition, each channel has a digital synchronous demodulator that demodulates the intermediate digital data-words in synchronism with the carrier signal providing demodulated data-words.

Abstract: A window comparator comprising a single comparator circuit that has a positive input, a differential negative input, and an output, wherein limits of a window are defined by a reference voltage and a window condition is defined for a differential voltage between a positive input voltage and a negative input voltage so that the differential voltage is within the limits of the window; including a common mode voltage, a first set of two switched capacitors connected to the positive comparator input, a second set of two switched capacitors connected to the negative comparator input, a switching array capable of assuming a plurality of different switching conditions, and detecting the output of the comparator in relation to the switching conditions of the switching array.

Abstract: A resolver arrangement that is inexpensive and yet offers high resolution and high noise rejection includes a carrier signal generator and two processing channels each of which has an analog input connected a different one of the stator coils and a channel output. Each of the processing channels includes a sigma-delta modulator with an output that supplies a bit-stream representative of an analog input signal received from a respective stator coil. Each channel also includes a first digital filter that receives the bit-stream from the sigma-delta modulator and converts the bit-stream to intermediate digital data-words. In addition, each channel has a digital synchronous demodulator that demodulates the intermediate digital data-words in synchronism with the carrier signal providing demodulated data-words.

Abstract: A method of providing a window comparator function with a single comparator unit that has a positive input cp, a differential negative input (cn) and an output (cout), wherein limits of a window are defined by a reference voltage (Vref) and a window condition is defined for a differential voltage between a positive input voltage (Vinp) and a negative input voltage (Vinn) so that the differential voltage is within the limits of the window, comprises the steps of providing a common mode voltage (Vmid), providing a first set of two switched capacitors (C1p, C2p) each of which has a first electrode connected to the positive input cp of the comparator unit, providing a second set of two switched capacitors (C1n, C2n) each of which has a first electrode connected to the negative input (cn) of the comparator unit, and providing a switching array capable of assuming a plurality of different switching conditions.