Patents by Inventor Mikael Bourges-Sevenier

Mikael Bourges-Sevenier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11941400
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example non-transitory computer readable storage medium includes instructions that, when executed, cause processor circuitry to at least identify a first code block having a first algorithmic purpose based on a second code block having a second algorithmic purpose, the second algorithmic purpose corresponding to the first algorithmic purpose, translate the first code block into executable domain specific language code, and output the executable domain specific language code.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Patent number: 11507838
    Abstract: Methods, apparatus, systems and articles of manufacture to optimize execution of a machine learning model are disclosed. An example apparatus includes a quantizer to quantize a layer of a model based on an execution constraint, the layer of the model represented by a matrix. A packer is to pack the quantized layer of the matrix to create a packed layer represented by a packed matrix, the packed matrix having non-zero values of the matrix grouped together along at least one of a row or a column of the matrix. A blocker is to block the packed layer into a blocked layer by dividing the non-zero values in the packed matrix into blocks. A fuser is to fuse the blocked layer into a pipeline. A packager is to package the pipeline into a binary.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 22, 2022
    Assignee: Intel Corporation
    Inventors: Mikael Bourges-Sevenier, Adam Herr, Sridhar Sharma, Derek Gerstmann, Todd Anderson, Justin Gottschlich
  • Publication number: 20220171626
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example non-transitory computer readable storage medium includes instructions that, when executed, cause processor circuitry to at least identify a first code block having a first algorithmic purpose based on a second code block having a second algorithmic purpose, the second algorithmic purpose corresponding to the first algorithmic purpose, translate the first code block into executable domain specific language code, and output the executable domain specific language code.
    Type: Application
    Filed: February 15, 2022
    Publication date: June 2, 2022
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Patent number: 11269639
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example apparatus includes a code lifter to identify annotated code corresponding to an algorithm to be executed on the heterogeneous system based on an identifier being associated with the annotated code, and convert the annotated code in the first representation to intermediate code in a second representation by identifying the intermediate code as having a first algorithmic intent that corresponds to a second algorithmic intent of the annotated code, a domain specific language (DSL) generator to translate the intermediate code in the second representation to DSL code in a third representation when the first algorithmic intent matches the second algorithmic intent, the third representation corresponding to a DSL representation, and a code replacer to invoke a compiler to generate an executable including variant binaries based on the DSL code.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Patent number: 11036477
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed improve utilization of a heterogeneous system executing software. The disclosed methods, apparatus, systems and articles of manufacture include an apparatus comprising a variant manager to determine whether an algorithm is a candidate for sub-algorithmic partitioning (SAP) based on at least one of a first size of input data to the algorithm and a second size of output data from the algorithm; a partitioner to partition the algorithm into at least a first tile and a second tile; and a compiler to compile a first variant based on the first tile and a second variant based on the second tile into an executable file, the first variant to be executed on a first processing element of the heterogeneous system, the second variant to be executed on a second processing element of the heterogeneous system.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 15, 2021
    Assignee: INTEL CORPORATION
    Inventors: Adam Herr, Sridhar Sharma, Mikael Bourges-Sevenier, Justin Gottschlich
  • Patent number: 10908884
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for runtime scheduling of software executing on a heterogeneous system. An example apparatus includes in response to a variant compiler to generate a representation of an algorithm in a domain-specific language (DSL), a compilation auto-scheduler to generate a schedule based on configurations for processing elements of the heterogeneous system, the processing elements including at least a first and a second processing element, the variant compiler to compile variant binaries based on the schedule, each of the variant binaries associated with the algorithm in the DSL, the variant binaries including a first variant binary corresponding to the first processing element and a second variant binary corresponding to the second processing element, and an application compiler to generate a fat binary including a runtime scheduler to select one or more of the variant binaries to execute a workload based on the schedule.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: February 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Publication number: 20190324755
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example apparatus includes a code lifter to identify annotated code corresponding to an algorithm to be executed on the heterogeneous system based on an identifier being associated with the annotated code, and convert the annotated code in the first representation to intermediate code in a second representation by identifying the intermediate code as having a first algorithmic intent that corresponds to a second algorithmic intent of the annotated code, a domain specific language (DSL) generator to translate the intermediate code in the second representation to DSL code in a third representation when the first algorithmic intent matches the second algorithmic intent, the third representation corresponding to a DSL representation, and a code replacer to invoke a compiler to generate an executable including variant binaries based on the DSL code.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 24, 2019
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Publication number: 20190325314
    Abstract: Methods, apparatus, systems and articles of manufacture to optimize execution of a machine learning model are disclosed. An example apparatus includes a quantizer to quantize a layer of a model based on an execution constraint, the layer of the model represented by a matrix. A packer is to pack the quantized layer of the matrix to create a packed layer represented by a packed matrix, the packed matrix having non-zero values of the matrix grouped together along at least one of a row or a column of the matrix. A blocker is to block the packed layer into a blocked layer by dividing the non-zero values in the packed matrix into blocks. A fuser is to fuse the blocked layer into a pipeline. A packager is to package the pipeline into a binary.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 24, 2019
    Inventors: Mikael Bourges-Sevenier, Adam Herr, Sridhar Sharma, Derek Gerstmann, Todd Anderson, Justin Gottschlich
  • Publication number: 20190317741
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed improve utilization of a heterogeneous system executing software. The disclosed methods, apparatus, systems and articles of manufacture include an apparatus comprising a variant manager to determine whether an algorithm is a candidate for sub-algorithmic partitioning (SAP) based on at least one of a first size of input data to the algorithm and a second size of output data from the algorithm; a partitioner to partition the algorithm into at least a first tile and a second tile; and a compiler to compile a first variant based on the first tile and a second variant based on the second tile into an executable file, the first variant to be executed on a first processing element of the heterogeneous system, the second variant to be executed on a second processing element of the heterogeneous system.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Adam Herr, Sridhar Sharma, Mikael Bourges-Sevenier, Justin Gottschlich
  • Publication number: 20190317880
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed improve runtime performance of software executing on a heterogeneous system. An example apparatus includes a feedback interface to collect a performance characteristic of the heterogeneous system associated with a compiled version of a block of code at a first runtime, the compiled version executed according to a function designating successful execution of the compiled version on the heterogeneous system, the heterogeneous system including a first processing element and a second processing element different than the first processing element; a performance analyzer to determine a performance delta based on the performance characteristic and the function; and a machine learning modeler to, prior to a second runtime, adjust a cost model of the first processing element based on the performance delta, the adjusted cost model to cause a reduction in the performance delta to improve runtime performance of the heterogeneous system.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Adam Herr, Sridhar Sharma, Mikael Bourges-Sevenier, Derek Gerstmann, Justin Gottschlich
  • Publication number: 20190317740
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for runtime scheduling of software executing on a heterogeneous system. An example apparatus includes in response to a variant compiler to generate a representation of an algorithm in a domain-specific language (DSL), a compilation auto-scheduler to generate a schedule based on configurations for processing elements of the heterogeneous system, the processing elements including at least a first and a second processing element, the variant compiler to compile variant binaries based on the schedule, each of the variant binaries associated with the algorithm in the DSL, the variant binaries including a first variant binary corresponding to the first processing element and a second variant binary corresponding to the second processing element, and an application compiler to generate a fat binary including a runtime scheduler to select one or more of the variant binaries to execute a workload based on the schedule.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Publication number: 20070192818
    Abstract: The aim of this invention is to provide a complete system to create, to deploy and to execute rich multimedia applications on various terminals and in particular embedded devices. A rich multimedia application is made of one or more media objects, being audio or visual, synthetic or natural, metadata, and their protection being composed and rendered on a display device over time in response to preprogrammed logic and user interaction. We describe the architecture of such a terminal, how to implement it on a variety of operating systems and devices, and how it executes downloaded rich, interactive, multi-media applications, and the architecture of such applications.
    Type: Application
    Filed: October 12, 2005
    Publication date: August 16, 2007
    Inventors: Mikael Bourges-Sevenier, Paul Collins
  • Publication number: 20050132385
    Abstract: A Scene Controller provides an interface between a multimedia terminal and an application so as to decouple application logic from terminal rendering resources and permits an application to modify the scene being drawn by the terminal during a frame. When the terminal is ready to render a frame, the terminal queries all SceneControllerListeners (from one or many applications) for any pending modifications to the scene being drawn. Each SceneControllerListener may execute modifications to the scene. When all modifications have been applied, the terminal finishes rendering the frame. Finally, the terminal queries each of the SceneControllerListeners for any post-rendering scene modifications. The scene may comprise a high-level description (e.g. a scene graph) or low-level graphical operations.
    Type: Application
    Filed: October 6, 2004
    Publication date: June 16, 2005
    Inventor: Mikael Bourges-Sevenier
  • Patent number: 6693645
    Abstract: An apparatus and method of processing a data file, by determining a range of values assumed by parameters in a hierarchy of nodes. The processing includes calculating a quantization parameter, based on an acceptable distortion level, indicating a desired number of bits, to represent the value range of each parameter for each node. Each node is examined to determine if a change in quantization parameter for a node parameter is desired, and if so a quantization parameter is inserted into the node. Then the hierarchy is reviewed, examining the quantization parameter at each node of the hierarchy and determining if one or more quantization parameters at a child node of the node being examined can be subsumed under the examined node quantization parameter. Quantization parameters are also used to encode animation data. The animation data, or frames, may be encoded into a sequence of Intra frames and Predictive frames. An Intra frame establishes quantization parameters used for subsequent predictive frames.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: February 17, 2004
    Assignee: iVast, Inc.
    Inventor: Mikael Bourges-Sevenier
  • Publication number: 20030097458
    Abstract: Four new nodes are proposed for an MPEG 4 audiovisual streaming data. Each of the nodes is encoded as a declarative operation in the scene data field of the MPEG 4 standard. The nodes are physics node, non-linear deformer node, MP4 movie texture node and camera sensor node. The physics node provides realistic behavior to geometry objects operating thereon in accordance with Newton's law. The non-linear deformer node permits a node to be tapered, twisted or bent. The MP4 movie texture node permits a visual element to be displayed in which a rectangular image has all pixels transparent and with some opaque pixels that define the video shape. Finally, a camera sensor node permits a virtual camera to be placed at a particular position of the audiovisual element having an orientation, a field of view and a fall-off parameter.
    Type: Application
    Filed: October 2, 2001
    Publication date: May 22, 2003
    Inventor: Mikael Bourges-Sevenier
  • Publication number: 20020083032
    Abstract: An apparatus and method of processing a data file, by determining a range of values assumed by parameters in a hierarchy of nodes. The processing includes calculating a quantization parameter, based on an acceptable distortion level, indicating a desired number of bits, to represent the value range of each parameter for each node. Each node is examined to determine if a change in quantization parameter for a node parameter is desired, and if so a quantization parameter is inserted into the node. Then the hierarchy is reviewed, examining the quantization parameter at each node of the hierarchy and determining if one or more quantization parameters at a child node of the node being examined can be subsumed under the examined node quantization parameter. Quantization parameters are also used to encode animation data. The animation data, or frames, may be encoded into a sequence of Intra frames and Predictive frames. An Intra frame establishes quantization parameters used for subsequent predictive frames.
    Type: Application
    Filed: November 30, 2000
    Publication date: June 27, 2002
    Inventor: Mikael Bourges-Sevenier
  • Publication number: 20020036639
    Abstract: An apparatus and method of processing an animation. An animation path is identified and segmented into at least one section. For each section of the animation path a non-linear parametric representation is determined to represent each section of the animation path. The non-linear representation is represented, or coded, in a virtual reality scene descriptive language. The scene descriptive language, containing the non-linear representation may be processed by receiving an initial scene description. Then specifying changes in the scene from the initial scene. Interpolating scenes between the initial value, and the changes from the initial value, by a non-linear interpolation process. The non-linear interpolation process may be performed by a non-linear interpolator in the scene descriptive language. Scenes may also be deformed by defining a sub-scene, of the scene, in a child node of the scene descriptive language.
    Type: Application
    Filed: January 29, 2001
    Publication date: March 28, 2002
    Inventor: Mikael Bourges-Sevenier