Abstract: A locking device for locking a turbine blade of a wind power plant at a predetermined pitch angle, which wind power plant includes a rotor hub and at least one turbine blade where the blade root of the at least one turbine blade is connected to the rotor hub through a pitch bearing so that the pitch angle of the at least one turbine blade is adjustable by turning of the at least one turbine blade about its longitudinal axis relative to the rotor hub and wherein the device for locking the turbine blade includes a mechanical snap-in mechanism which in a locked position prevents the at least one turbine blade from turning about its longitudinal axis thus fixating the at least one turbine blade in the predetermined pitch angle.

Abstract: The present invention comprises a processed thin film substrate (10) and a method therefore, in order to produce a flexible printed circuit card, having a plurality of microvias going or passing through the thin film substrate and electrically connected along faced-away surfaces, in order to form an electric circuit. A first a number of real nano-tracks are filled with a first material (M1) having good electric properties, for the formation of a first number of, here denominated, first vias (V10, V30, V50), that a second number of real nano-tracks are filled with a second material (M2), having good electric properties, for the formation of a second number of, here denominated, second vias (V20, V40, V60). The first material (M1) and the second material (M2) of said first and second vias (V10-V60) are chosen having mutually different thermoelectric properties.

Abstract: Wind power plant with a wind turbine with a turbine shaft with which a generator shaft, which can be an extension of the turbine shaft, is connected to the rotor (12) of an electric generator. The rotor is radially surrounded by a stator, the turbine shaft is journalled in two bearing housings with bearings arranged on a base at the top of a tower, the base is pivotable around a vertical axis, and a motor is provided to effect the pivoting. The generator shaft is integrated with or rigidly connected to a flexing turbine shaft, the stator and rotor are carried by the generator shaft, to allow the generator to follow the flexing movement of the turbine shaft and the stator is locked against turning by a non-rotatable coupling which transfers substantially no bending moment or axial force acting against the flexing of the turbine shaft due to the bending moment acting on the turbine shaft from its hub, the bearings being provided to allow flexing of the turbine shaft.

Abstract: A semiconductor arrangement is provided for generating a predetermined time delay. Two clocks are connected to two parallel, redundant semi-conductor circuits emitting clock signals from multiplexers. The redundant circuits receive delayed clock signals from one of the clocks, and from the other clock, clock signals that are delayed in adjustable delay circuits to be phased in with the clock signals from the first clock. A number of delay elements and a first reference number of delay elements, providing a predetermined delay time, are connected in a reference delay circuit. A quotient of the two numbers is stored. One of the semi-conductor circuits is replaced by an alternative semi-conductor circuit, the reference delay circuit of which is set on the predetermined delay time, corresponding to a second reference number of delay elements. An adjustable delay circuit is set on the same delay time as the replaced semi-conductor circuit by means of the second reference number and the quotient.

Abstract: A system and method of preventing metastability in conjunction with the receipt in a first clock domain of an asynchronous digital signal from a second clock domain when the first domain operates with a first clock frequency, and the second domain operates with a second clock frequency that is known within the first domain. The first domain sends information to the second domain, and includes a reference signal containing phase information known in the first domain. The information is clocked into the second domain utilizing the reference information. The second domain then sends the asynchronous digital signal to the first clock domain. A receiving unit in the first domain determines the phase information from the received signal with a known degree of maximum uncertainty that is less than one period of the reference signal. The first domain then stably reads the received asynchronous digital signal.

Abstract: Wind power plant with a wind turbine with a turbine shaft (8) which with a generator shaft (22), which can be an extension of the turbine shaft, is connected to the rotor (12) of an electric generator (11). The turbine shaft (8) is journalled in two bearing housings (6, 7) with bearings (9, 10) arranged on a base (4) at the top of a tower (1). The generator shaft (22) is integrated with or rigidly connected to flexing turbine shaft (8). The stator (19) and rotor (12) are carried by the generator shaft (22), to allow the generator (11) to follow the flexing movement of the turbine shaft (8), the stator (19) is locked against turning by a non-rotatable coupling (20) which transfers substantially no bending movement or axial force acting against the flexing of the turbine shaft (8) due to the bending movement acting on the turbine shaft (8) from its hub, the bearings (9 and 10) being provided to allow flexing of the turbine shaft.

Abstract: The figure shows a unit (5) for distributing clock signals (SA1, SB1) in telecommunication systems. The unit is provided with a semiconductor arrangement (ADA, CTA, RDA) for generating a predetermined time delay. Two clocks (CLA, CLB) are connected to two parallel, redundant semi-conductor or circuits (SCA, SCB) emitting clock signals (SA2, SB2) from multiplexers (MXA, MXB). These receive delayed clock signals (SA1) from one of the clocks (CLA), and from the other clock (CLB) clock signals (SB1) that are delayed in adjustable delay circuits (ADA, ADB) to be phased in with the clock signals (SA1) from the first clock Thus, a number of delay elements in the delay circuit (ADA) are connected and a first reference number of delay elements, providing a predetermined delay time, are connected in a reference delay circuit (RDA). A quotient of the two numbers is stored.

Abstract: A pulse detector detects if a clock pulse signal is in phase with a reference clock pulse signal in an efficient manner with very high accuracy. The pulse detector includes a first delay unit adapted to receive an input clock pulse signal and to delay the input clock pulse signal by a first pre-specified delay for output as output clock pulse signal, and a second delay unit adapted to delay the output clock pulse signal by a second pre-specified delay. A sampling unit is adapted to sample the input clock pulse signal and the output of the second delay unit at a sampling time defined by a reference clock pulse signal and to output the samples for phase delay indication.

Abstract: A fault tolerant processing system includes at least two processing planes. Each processing plane processes an input signal and generates an output signal. The system further includes plane termination logic for receiving the output signals of the processing planes to generate a non-redundant output signal. Each processing plane is provided with devices for detecting a fault in the plane, and devices for substituting, in response to detection of a fault in the plane, a signal component, referred to as control component, representing a predetermined logical state for each one of those components of the processed input signal that are affected by the detected fault. Furthermore, the plane termination logic includes devices for performing logical operations on the output signals of the planes such that, in the generation of the non-redundant output signal, unaffected signal components of a received signal override corresponding control components of another received signal.

Abstract: In a general switch, a word oriented switch and a bit oriented switch are connected such that a common input signal included data appearing in time slots is provided to both switches. The general switch further includes a device for establishing, for each one of a number of outgoing time slots, at least one of a first connection path through the word oriented switch and a second connection through the bit oriented switch, and a device for selecting, for each outgoing time slot, data from an established one of the connection path. For each outgoing time slot, only one of the connection paths is established and the selecting device selects data from the established connection path.

Abstract: A method and system for testing a memory in operation. A storage unit is used to temporarily free one memory location in the memory, making it possible to check this memory location for bit errors. Data intended for the selected memory location is stored in the storage unit, and instead a test pattern is written into the memory location to be tested and read out again, all in coordination with the normal operation of the memory. If the pattern read from the test location does not match the written test pattern, an alarm is raised.

Abstract: In a switch structure for circuit switching, part of the space switch functionality of a time-space (TS) switch core is broken out and arranged in groups of switch adapter boards, and the TS-switch core itself is divided into a matrix of smaller and independent TS-modules that are associated with the switch adapter boards. Each group of switch adapter boards is co-operating with a predetermined row of TS-modules in the matrix for input of data to the TS-modules in that row, and with a predetermined column of TS-modules in the matrix for output of data from the TS-modules of that column. In this way, it is possible to implement the switch structure into a number of subracks with a reasonable number of interconnections between different subracks, thus obtaining a truly modular TS-switch structure.

Abstract: A clock pulse degradation detector monitors the leading and trailing edges of the monitored clock pulse train, and determines the number of leading and trailing edges of the supervised clock pulse train occurring within a single reference pulse. An external oscillator provides an external signal to a reset generator that develops reference pulses having a period less than that of a full cycle of the supervised clock pulse train, but longer than either a single pulse or land of the monitored clock pulse train. Based upon the number of leading and trailing edges detected in the supervised pulse train, a determination is made as to whether the supervised clock train is regular or irregular. Preferably, a pair of two-bit shift registers are utilized to accumulate the number of leading and trailing edges of the supervised clock pulse train. Logic is utilized to determine whether the number of leading and trailing edges stored within these two-bit shift registers indicate a regular or irregular clock pulse train.

Abstract: To detect if a clock pulse signal is in phase with a reference clock pulse signal in an efficient manner with very high accuracy there is proposed a pulse detector, comprising a first delay unit (12) adapted to receive an input clock pulse signal (&phgr;(t)) and to delay the input clock pulse signal (&phgr;(t)) by a first pre-specified delay (d1) for output as output clock pulse signal (&phgr;out(t)) and a second delay unit (14) adapted to delay the output clock pulse signal (&phgr;out(t)) by a second pre-specified delay (d2). A sampling unit (16) is adapted to sample the input clock pulse signal (&phgr;(t)) and the output of the second delay unit (14) (&phgr;out(t−d1−d2)) at a sampling time defined by a reference clock pulse signal (&phgr;R(t)) and to output the samples (v1, v2) for phase delay indication.

Abstract: A plurality of input signals are switched in an apparatus including redundant switching planes and hardware for receiving an output signal from each of the redundant switching planes. Each switching plane is for switching the plurality of input signals, and each switching plane includes at least two switching modules, each switching module being connected to receive a subset of the input signals directly from an input signal source coupled to the apparatus. Each switching module is further connected to receive a remaining subset of the input signals from remaining switching modules on the same switching plane; and each switching module generates an output signal having components selected from the plurality of input signals. To improve performance in the event of a double fault, each switching module detects whether any of the remaining switching modules on the same switching plane are faulty.