Patents by Inventor Mikael Peltier

Mikael Peltier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8024716
    Abstract: A system comprising a compiler that compiles source-level code to generate an intermediate-level instruction comprising a predetermined component. The intermediate-level instruction is an at least partially optimized version of the source-level code. Execution of the predetermined component triggers the execution of a series of instructions that, when executed, generates previously-unavailable data that is used to re-generate the intermediate-level instruction. The re-generated intermediate-level instruction has a length less than or equal to that of the intermediate-level instruction.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: September 20, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Jean-Philippe Lesot, Mikael Peltier, Gilbert Cabillic
  • Patent number: 7757223
    Abstract: The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic of a processor, trigger execution of a first series of instructions by the decode logic that pops a first value off of a data structure, such as a stack or local variable map, the first value indicative of a parameter type pushed on the stack or local variable map by a previously decoded instruction; and verify that the first value is a parameter type expected by the first instruction.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: July 13, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Gilbert Cabillic, Jean-Philippe Lesot, Mikael Peltier, Gerard Chauvel
  • Patent number: 7624382
    Abstract: A method and system to build a control flow graph by execution of micro-sequences using hardware. Some illustrative embodiments are a processor comprising fetch logic that retrieves an instruction from a memory, the instruction being part of a program, and decode logic coupled to the fetch logic which decodes the instruction, wherein the instruction decoded by the decode logic triggers execution of a micro-sequence to enter the instruction in a control flow graph.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: November 24, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Jean-Philippe Lesot, Gilbert Cabillic, Mikael Peltier
  • Publication number: 20060026404
    Abstract: The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic of a processor, trigger execution of a first series of instructions by the decode logic that pops a first value off of a data structure, such as a stack or local variable map, the first value indicative of a parameter type pushed on the stack or local variable map by a previously decoded instruction; and verify that the first value is a parameter type expected by the first instruction.
    Type: Application
    Filed: July 25, 2005
    Publication date: February 2, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Gilbert Cabillic, Jean-Philippe Lesot, Mikael Peltier, Gerard Chauvel
  • Publication number: 20060026571
    Abstract: A method and system to build a control flow graph by execution of micro-sequences using hardware. Some illustrative embodiments are a processor comprising fetch logic that retrieves an instruction from a memory, the instruction being part of a program, and decode logic coupled to the fetch logic which decodes the instruction, wherein the instruction decoded by the decode logic triggers execution of a micro-sequence to enter the instruction in a control flow graph.
    Type: Application
    Filed: July 26, 2005
    Publication date: February 2, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Gilbert Cabillic, Jean-Philippe Lesot, Mikael Peltier, Gerard Chauvel
  • Publication number: 20060026574
    Abstract: A system comprising a compiler that compiles source-level code to generate an intermediate-level instruction comprising a predetermined component. The intermediate-level instruction is an at least partially optimized version of the source-level code. Execution of the predetermined component triggers the execution of a series of instructions that, when executed, generates previously-unavailable data that is used to re-generate the intermediate-level instruction. The re-generated intermediate-level instruction has a length less than or equal to that of the intermediate-level instruction.
    Type: Application
    Filed: July 26, 2005
    Publication date: February 2, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Jean-Philippe Lesot, Mikael Peltier, Gilbert Cabillic
  • Publication number: 20060026580
    Abstract: A method and related system of dynamic compiler resolution. Some of the illustrative embodiments are a computer-implemented method comprising compiling a source file containing an application program (the compiling creates a destination file containing a compiled version of the application program), and inserting in the compiled version of the application program a series of commands that (when executed at run time of the application program) generate an optimized code portion using a value available at run time.
    Type: Application
    Filed: July 26, 2005
    Publication date: February 2, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Gilbert Cabillic, Mikael Peltier, Jean-Philippe Lesot