Abstract: An integrated circuit is provided with interface circuitry used to provide an interface between functional circuitry of the integrated circuit and components external to the integrated circuit. The functional circuitry is configured to operate from a first power supply and has a power supply distribution network associated therewith providing the first power supply to the functional components of the functional circuitry. The interface comprises a plurality of interface cells that have interface components operating from a second power supply different to the first power supply. A power supply line structure is shared by the plurality of interface cells, and arranged to provide the second power supply to the interface components. In addition, at least a subset of the interface cells include additional interface components that operate from the first power supply.

Abstract: An integrated circuit is provided with interface circuitry used to provide an interface between functional circuitry of the integrated circuit and components external to the integrated circuit. The interface circuitry includes a plurality of interface cells having interface components configured to operate from a first power supply. Each interface cell incorporates a power supply line section extending across its width and configured to cooperate with power supply line sections of other interface cells to provide a power supply line structure shared by the plurality of interface cells, for provision of the first power supply to the interface components. Each power supply line section includes a first supply line portion and a second supply line portion, the first supply line portion being sized to support a current carrying constraint of the interface circuitry, whilst the second supply line portion is sized insufficiently to support that current carrying constraint.

Abstract: Circuitry comprises a high voltage rail providing a high voltage level corresponding to a higher voltage domain, an intermediate voltage source, a low voltage rail, and devices that operate in a lower voltage domain. First devices in an upper voltage region are powered between the high voltage rail and an intermediate voltage rail powered by the intermediate source. Second devices in a lower voltage region are powered between the intermediate and low rails. On power up, the intermediate source is powered before the high voltage rail. An isolating circuit connects the intermediate source to a node when the high voltage rail is powered and isolates the node from the intermediate source when the high voltage rail is not powered to impede current flow from the intermediate source to the high voltage rail.

Abstract: Level shifting circuitry comprises a first level shifter and a second level shifter. In response to a falling edge transition of an input signal, the first level shifter generates a primary transition of a first intermediate signal faster than the second level shifter generates a secondary transition of a second intermediate signal. In response to a rising edge of the input signal, the second level shifter generates a primary transition of the second intermediate signal faster than the first level shifter generates a secondary transition of the first intermediate signal. Output switching circuitry is provided to switch an output signal between an output high voltage level and an output low voltage level in response to the primary transition of the first intermediate signal and the primary transition of the second intermediate signal.

Abstract: Circuitry, operating in a high voltage domain, including a high and low voltage inputs, and including a plurality of devices designed to operate optimally powered in a native voltage domain that is lower voltage than said high voltage domain and some devices arranged in two sets. The circuitry including a further input for receiving the high native voltage level. Each set having at least one device, a first set being arranged to receive an intermediate low reference voltage level as a low voltage level signal and the high voltage level as a high voltage level signal and the second set being arranged to receive the high native voltage level as a high voltage level signal and the low voltage level as a low voltage level signal. The intermediate low reference voltage level includes a voltage level generated by subtracting the high native voltage level from the high voltage level.

Abstract: A cascoded input-output device is provided configured to receive at an input node a lower voltage input signal and to generate at an output node a higher voltage output signal. The input-output device is split into two voltage domains to enable output signals in a larger range to be generated, while the components of the input-output device individually operate in a smaller range. By applying a selected bias voltage to a protected node of the cascoded input-output device, first changing that selected bias voltage in response to a transition of the input signal and then switching that selected bias voltage back when the output signal reaches a predetermined level, that node is protected, either avoiding stress-inducing voltage swings or providing a switching speed increasing charge boost.

Abstract: Level shifting circuitry comprises a first level shifter and a second level shifter. In response to a falling edge transition of an input signal, the first level shifter generates a primary transition of a first intermediate signal faster than the second level shifter generates a secondary transition of a second intermediate signal. In response to a rising edge of the input signal, the second level shifter generates a primary transition of the second intermediate signal faster than the first level shifter generates a secondary transition of the first intermediate signal. Output switching circuitry is provided to switch an output signal between an output high voltage level and an output low voltage level in response to the primary transition of the first intermediate signal and the primary transition of the second intermediate signal.

Abstract: A power supply cell for distributing power supplied from a first voltage supply to an integrated circuit is disclosed.

Abstract: Circuitry is disclosed that comprises: a high voltage rail for providing a high voltage level corresponding to a first higher voltage domain; an intermediate voltage source, a low voltage rail; and a plurality of devices configured to operate in a second lower voltage domain; said circuitry being configured such that a first set of said plurality of devices are arranged in an upper voltage region where they are powered between said high voltage rail and an intermediate voltage rail powered by said intermediate voltage source and a second set of said plurality of devices are arranged in a lower voltage region where they are powered between said intermediate voltage rail and said low voltage rail, said circuitry being configured such that on power up said intermediate voltage source is powered before said high voltage rail, said circuitry further comprising: an isolating circuit arranged in said upper voltage region, said isolating circuit comprising at least one switching device for connecting said intermediat

Abstract: A cascoded input-output device is provided configured to receive at an input node a lower voltage input signal and to generate at an output node a higher voltage output signal. The input-output device is split into two voltage domains to enable output signals in a larger range to be generated, whilst the components of the input-output device individually operate in a smaller range. By applying a selected bias voltage to a protected node of the cascoded input-output device, first changing that selected bias voltage in response to a transition of the input signal and then switching that selected bias voltage back when the output signal reaches a predetermined level, that node is protected, either avoiding stress-inducing voltage swings or providing a switching speed increasing charge boost.

Abstract: A power supply cell for distributing power supplied from a first voltage supply to an integrated circuit is disclosed.

Abstract: A buffer circuit for transmission of logical signals includes a first buffer and second buffer. The first buffer supplies logical signals to the output buffer which is connected in series with the first buffer to produce output logical signals. A slope of the logical signals produced at the output of the output buffer is controlled in order to adapt the signal transmission speed. The first buffer and output buffer preferably are logic gates (such as inverters) made using the CML technology. The slope of the output signal is controlled using a slope control module which applies a logical signal which programs a resistance value of a pair of variable output resistances of the CML logic gate which forms the first buffer.