Patents by Inventor Mike Augustin

Mike Augustin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for determining which timing sets to pre-load into the pin electronics of a circuit test system, and for pre-loading or storing said timing sets
    Patent number: 7502974
    Abstract: In one embodiment, a method includes, providing a test program designed to control a circuit test system. The circuit test system has a plurality of test channels, each test channel of which is configured to be selectively coupled to a plurality of sub-channels under control of the test program. The method further includes 1) analyzing the test program to determine what combinations of channels, sub-channels and timing sets are required by the test program, and 2) in response to this analysis, creating a map of which timing sets, for which combinations of channels and sub-channels, should be pre-loaded into pin electronics that correspond to the test channels.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: March 10, 2009
    Assignee: Verigy (Singapore) Pte. Ltd.
    Inventors: Preeti Garg, Romi Mayder, Mike Augustin
  • Method and apparatus for determining which timing sets to pre-load into the pin electronics of a circuit test system, and for pre-loading or storing said timing sets
    Publication number: 20070220387
    Abstract: In one embodiment, a method includes, providing a test program designed to control a circuit test system. The circuit test system has a plurality of test channels, each test channel of which is configured to be selectively coupled to a plurality of sub-channels under control of the test program. The method further includes 1) analyzing the test program to determine what combinations of channels, sub-channels and timing sets are required by the test program, and 2) in response to this analysis, creating a map of which timing sets, for which combinations of channels and sub-channels, should be pre-loaded into pin electronics that correspond to the test channels.
    Type: Application
    Filed: February 22, 2006
    Publication date: September 20, 2007
    Inventors: Preeti Garg, Romi Mayder, Mike Augustin