Abstract: A flash memory comprises an address bus, a data bus, control lines, and an array of addressable nonvolatile memory cells, connected to the address bus and the data bus. A latch, activated by control signals, stores signals supplied from the address bus or the data bus. A decoder decodes the signal stored in the latch, and in response to a first signal decoded for partitioning the array of memory cells into a plurality of first sectors each having a first size, and in response to a second signal decoded for partitioning the array of memory cells into a plurality of second sectors each of a second size, different from the first size. A control circuitry controls the erasure of a first or a second sector of the memory array in response to the first or second signal decoded.