Abstract: Previously, drilled vias were formed in multilayer substrates, interconnecting all layers. The positioning of flip chip bump pads on the substrate has been non-determinate. With the more recent use of microvias, which connect only two adjacent layers, non-determinate positioning of bump pads results in inefficient connection and reduces the routing efficiency and electrical performance. By designating the position of the power and ground bump pads on the substrate, microvias connect the bump pads directly to the related power or ground plane. Similarly signal bump pads can be directly connected to signal planes, giving improved routing and electrical performance. The signal, power and ground bump pads are in sequential rows, to match the relative positioning of the signal, power and ground planes.

Abstract: A substrate structure, such as is used for printed circuit boards and printed circuit board based substrates for semiconductor devices comprises two PCB core layers with at least one laminate layer between the PCB core layers. Improved electrical performance is obtained and strip line configuration can be used to as compared to microstrip configuration with conventional structures. A reduction in high-frequency power distribution impediance is obtained and smaller parasitic parameters.

Abstract: Thin organic layers are laminated on both the top and bottom of a relatively thin ceramic layer to form a reliable thinner composite substrate for packaging a chip-scale flip-chip die in a thin package. A semiconductor die has a number of solder bump-mounting pads formed thereupon which are connected with solder bumps to mounting pads on the top surface of the thin composite substrate.

Abstract: Provided is a semiconductor flip chip die metal layout which provides a flat UBM where surface metal pads are narrower than UBMs in order to accommodate decreased die pitch. This is achieved by depositing a metal region adjacent to and closely spaced from the pad which, together with the pad, is capable of providing a substrate that will result in a substantially flat passivation layer surface on which the UBM is subsequently deposited. The adjacent closely spaced metal region may be provided by bringing metal traces closer to a reduced size surface metal pad (into the die surface area underlying the UBM), and/or by depositing dummy metal similarly near the pad. The dummy metal may also be deposited over the whole chip surface area not occupied by other electrical components.

Abstract: A package for mounting a semiconductor device to a circuit board. An insulating substrate is provided, which has at least one layer, and provides rigidity to the package. A plurality of electrically conductive contacts are disposed on the top surface of the substrate, receive the semiconductor device, and make electrical contact between the semiconductor device and the substrate. A plurality of electrically conductive through-holes are formed in the substrate, and extend from the top surface of the substrate to the bottom surface of the substrate. The through-holes make electrical connection between all of the layers of the substrate. Electrical interconnections between the contacts and the through-holes are provided by a plurality of electrically conductive traces. A z-conductive layer is attached to the bottom surface of the substrate.

Abstract: A substrate, an alignment plate, a heat sink, a back plate, a plurality of spacers, and a plurality of nuts are used to removably package one or more semiconductor package into a single module. The semiconductor dies are packaged with tape automated bonding (TAB) packages having land grid array (LGA) outer lead bumps. The substrate comprises a number of land patterns, a number of alignment cavities, and a number of join cavities. The alignment plate is fabricated with a number of alignment pins, a number of housing cavities, and a number of join cavities. The heat sink is fabricated with a number of stems and a number of join cavities. The back plate is fabricated with a number of extrusions having threaded ends. The spacers are fabricated with ranged openings at both ends, and each spacer is loaded with a number of spring washers. The nuts are fabricated with stepped heads.

Abstract: A substrate, an alignment plate, a heat sink, a back plate, a plurality of spacers, and a plurality of nuts are used to removably package one or more semiconductor package into a single module. The semiconductor dies are packaged with tape automated bonding (TAB) packages having land grid array (LGA) outer lead bumps. The substrate comprises a number of land patterns, a number of alignment cavities, and a number of join cavities. The alignment plate is fabricated with a number of alignment pins, a number of housing cavities, and a number of join cavities. The heat sink is fabricated with a number of stems and a number of join cavities. The back plate is fabricated with a number of extrusions having threaded ends. The spacers are fabricated with flanged openings at both ends, and each spacer is loaded with a number of spring washers. The nuts are fabricated with stepped heads.

Abstract: A package for mounting a semiconductor device to a circuit board. An insulating substrate is provided, which has at least one layer, and provides rigidity to the package. A plurality of electrically conductive contacts are disposed on the top surface of the substrate, receive the semiconductor device, and make electrical contact between the semiconductor device and the substrate. A plurality of electrically conductive through-holes are formed in the substrate, and extend from the top surface of the substrate to the bottom surface of the substrate. The through-holes make electrical connection between all of the layers of the substrate. Electrical interconnections between the contacts and the through-holes are provided by a plurality of electrically conductive traces. A z-conductive layer is attached to the bottom surface of the substrate.

Abstract: A film of elastomeric material is used to laminate the tape with LGA outer lead bumps to the stiffner plate of the semiconductor package. The elastomeric material has the necessary physical and electrical characteristics to provide the required firmness to maintain good electrical contact between the outer lead bumps and the corresponding contacting pads on a socket, ceramic substrate or PWB, and at the same time, to provide the required resilience to accommodate differences in heights between the outer lead bumps. The stiffner plate is fabricated with a cavity at its center for accommodating the VLSI die, and slots along the outer edges of its underside for storing the excess elastomeric material squeezed out when laminating the tape to the stiffner plate, thereby preventing the excess squeezed out elastomeric material from building up at the outer edges of the semiconductor package to a height in excess of the outer lead bumps.

Abstract: A liquid cooling module for semiconductor chips is disclosed. The module includes a plurality of substrates, each containing at least one chip. The substrates are arranged in the module so that when coolant flows through the module, the coolant is exposed to the top and bottom surfaces of the chips. A gasket is used between each substrate. The gasket is made if a Z-axis elastromeric material that is impervious to liquid and therefore directs the flow of the coolant in the module and makes the module liquid tight. The material also is conductive in the Z direction, but not the X or Y direction, thereby making electrical communication between the chips on different substrate levels possible. The module is intended to be attached to a circuit board, thus simplifying the layout of liquid cooled chips on the board.