Abstract: A circuit and system for improving signal integrity in a memory system. The circuit has a transmission line having a dampening impedance between a driver and a branch point of the transmission line. The circuit also has a termination impedance having one end coupled to the transmission line between the dampening impedance and the branch point. The transmission line has branches coupled to memory module interfaces. The branches have respective lengths between the branch point and the memory module interfaces to be configured symmetrically, wherein the branch point is at a point to balance signal transmission on the branches.

Abstract: System and methods of selectively managing errors in memory modules. In an exemplary implementation, a method may include monitoring for persistent errors in the memory modules. The methods may also include mapping at least a portion of the memory modules to a spare memory cache only to obviate persistent errors. The method may also include initiating memory erasure on at least a portion of the memory modules only if insufficient cache lines are available in the spare memory cache.

Abstract: A double-high memory system compatible with termination schemes for single-high memory systems. The system includes an interface for input and output of data. A plurality of memory units is configured in two rows. A transmission line couples the plurality of memory units and the interface. The double-high memory system is provided in a non-stacked arrangement.

Abstract: A double-high memory system compatible with termination schemes for single-high memory systems. The system includes an interface for input and output of data. A plurality of memory units is configured in two rows. A transmission line couples the plurality of memory units and the interface. The double-high memory system is provided in a non-stacked arrangement.

Abstract: A circuit and system for improving signal integrity in a memory system. The circuit has a transmission line having a dampening impedance between a driver and a branch point of the transmission line. The circuit also has a termination impedance having one end coupled to the transmission line between the dampening impedance and the branch point. The transmission line has branches coupled to memory module interfaces. The branches have respective lengths between the branch point and the memory module interfaces to be configured symmetrically, wherein the branch point is at a point to balance signal transmission on the branches.

Abstract: A present invention termination stub system is disclosed. In one embodiment the termination stub system includes a first resistor, a division point, and a second resistor. The first resistor dampens reflections of a signal and is in series with an input signal path. The division point is coupled to the first resistor. The division point divides the signal into a plurality of output communication paths. The second resistor balances resistance of the termination stub system with a characteristic impedance of the signal input path. The second resistor is coupled to the first resistor in parallel with the input signal path and the plurality of output communication paths.

Abstract: A circuit and system addressing multiple computer memory modules on the same bus while maintaining proper timing. The circuit includes a transmission line having a dampening impedance between a driver and a branch point of the transmission line. The circuit also has a termination impedance having one end coupled to the transmission line between the dampening impedance and the branch point. The transmission line has branches from the branch point. Individual branches are coupled to at least one memory module interface.