Patents by Inventor Mike Cornaby

Mike Cornaby has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10642744
    Abstract: An improved architectural means to address processor cache attacks based on speculative execution defines a new memory type that is both cacheable and inaccessible by speculation. Speculative execution cannot access and expose a memory location that is speculatively inaccessible. Such mechanisms can disqualify certain sensitive data from being exposed through speculative execution. Data which must be protected at a performance cost may be specifically marked. If the processor is told where secrets are stored in memory and is forbidden from speculating on those memory locations, then the processor will ensure the process trying to access those memory locations is privileged to access those locations before reading and caching them. Such countermeasure is effective against attacks that use speculative execution to leak secrets from a processor cache.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 5, 2020
    Assignee: NVIDIA Corporation
    Inventors: Darrell D. Boggs, Ross Segelken, Mike Cornaby, Nick Fortino, Shailender Chaudhry, Denis Khartikov, Alok Mooley, Nathan Tuck, Gordon Vreugdenhil
  • Publication number: 20190004961
    Abstract: An improved architectural means to address processor cache attacks based on speculative execution defines a new memory type that is both cacheable and inaccessible by speculation. Speculative execution cannot access and expose a memory location that is speculatively inaccessible. Such mechanisms can disqualify certain sensitive data from being exposed through speculative execution. Data which must be protected at a performance cost may be specifically marked. If the processor is told where secrets are stored in memory and is forbidden from speculating on those memory locations, then the processor will ensure the process trying to access those memory locations is privileged to access those locations before reading and caching them. Such countermeasure is effective against attacks that use speculative execution to leak secrets from a processor cache.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 3, 2019
    Inventors: Darrell D. BOGGS, Ross SEGELKEN, Mike CORNABY, Nick FORTINO, Shailender CHAUDHRY, Denis KHARTIKOV, Alok MOOLEY, Nathan TUCK, Gordon VREUGDENHIL
  • Patent number: 8397090
    Abstract: Methods and apparatus to operate various logic blocks of an integrated circuit (IC) at independent voltages are described. In one embodiment, supply of power to one or more domains in an IC is adjusted based on an indication that power consumption by components of the corresponding domain is to be modified. Other embodiments are also described.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: March 12, 2013
    Assignee: Intel Corporation
    Inventors: Stephen H. Gunther, Edward Burton, Anant Deval, Stephan Jourdan, Robert Greiner, Mike Cornaby
  • Publication number: 20080136397
    Abstract: Methods and apparatus to operate various logic blocks of an integrated circuit (IC) at independent voltages are described. In one embodiment, supply of power to one or more domains in an IC is adjusted based on an indication that power consumption by components of the corresponding domain is to be modified. Other embodiments are also described.
    Type: Application
    Filed: December 8, 2006
    Publication date: June 12, 2008
    Inventors: Stephen H. Gunther, Edward Burton, Anant Deval, Stephan Jourdan, Robert Greiner, Mike Cornaby