Patents by Inventor Mike Duh

Mike Duh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7411906
    Abstract: A method for optimizing frequency of a clock signal is provided for operations of a network switch. The network switch includes a clock signal generator for generating the clock signal, and a plurality of input/output ports for communicating therevia with at least one network node. Firstly, a control signal is asserted to the clock signal generator according to a certain condition of the input/output ports, e.g. the count of the I/O ports in use or the overall data transmission rate of the I/O ports in use. Then, the frequency of the clock signal outputted from the clock signal generator is adjusted in response to the control signal.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: August 12, 2008
    Assignee: Via Technologies, Inc.
    Inventors: Hsi-Chih Peng, Mike Duh
  • Publication number: 20040218634
    Abstract: A method for optimizing frequency of a clock signal is provided for operations of a network switch. The network switch includes a clock signal generator for generating the clock signal, and a plurality of input/output ports for communicating therevia with at least one network node. Firstly, a control signal is asserted to the clock signal generator according to a certain condition of the input/output ports, e.g. the count of the I/O ports in use or the overall data transmission rate of the I/O ports in use. Then, the frequency of the clock signal outputted from the clock signal generator is adjusted in response to the control signal.
    Type: Application
    Filed: March 12, 2004
    Publication date: November 4, 2004
    Inventors: Hsi-Chih Peng, Mike Duh
  • Publication number: 20040030970
    Abstract: A test platform device for testing an embedded memory of a system on chip includes a first socket, a second socket and a test control circuit. The first socket is used for plugging therein the system on chip to be tested. The second socket is used for plugging therein an independent memory chip. The test control circuit is electrically connected to the first socket and the second socket, performs a comparable writing-reading operation of each of the embedded memory of the system on chip and the independent memory chip and outputting an error data when incomparable results are obtained in response to the comparable writing-reading operation of each of the embedded memory of the system on chip and the independent memory chip.
    Type: Application
    Filed: May 7, 2003
    Publication date: February 12, 2004
    Inventors: Murphy Chen, Timothy Tseng, Chao-Cheng Cheng, Ruth Lin, Mike Duh