Patents by Inventor Mike Erickson

Mike Erickson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140244874
    Abstract: A logic module for restoring stability to an unstable bus. The logic module includes logic for detecting that a communications error has occurred on the bus. The logic module also includes logic for stabilizing a slave device operating in a read mode. The logic module further includes logic for stabilizing the slave device operating in a write mode. The stabilizing of the slave device operating in a write mode occurs after stabilizing the slave device operating in a read mode.
    Type: Application
    Filed: May 7, 2014
    Publication date: August 28, 2014
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Mike Erickson, David Maciorowski
  • Patent number: 8799545
    Abstract: A method for restoring stability to an unstable bus includes cycling a clock of the bus a number of times, transmitting a stop bit, cycling a clock line of the bus at least one time and transmitting a stop bit immediately after an acknowledgment bit has been received by a bus master.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: August 5, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mike Erickson, David Maciorowski
  • Publication number: 20120331196
    Abstract: A method for restoring stability to an unstable bus includes cycling a clock of the bus a number of times, transmitting a stop bit, cycling a clock line of the bus at least one time and transmitting a stop bit immediately after an acknowledgment bit has been received by a bus master.
    Type: Application
    Filed: February 26, 2010
    Publication date: December 27, 2012
    Inventors: Mike Erickson, David Maciorowski
  • Publication number: 20110145655
    Abstract: Example apparatus and methods virtualize a circuit disposed between an input/output (I/O) hub and an I/O device. The I/O hub is configured to communicate PCIe slot control and status signals with an I/O device via an interface. The example apparatus and methods selectively intercept and transform signals passing between the I/O hub and the I/O device. The example apparatus and methods may also provide intercepted signals to a sideband monitor.
    Type: Application
    Filed: December 11, 2009
    Publication date: June 16, 2011
    Inventors: Mike ERICKSON, David MACIOROWSKI
  • Publication number: 20060209507
    Abstract: A media holding device for connecting an electronic component to a computer is described herein. An embodiment of the device comprises a bay comprising a bay first side and a bay second side, wherein the electronic component is receivable in the bay first side. The media holding device may also comprise a first circuit comprising a first connector and a second connector. The first connector is located proximate the bay second side. A third connector associated with the electronic component is connectable to the first connector when the electronic component is received within the bay. A connector associated with the computer is connectable to the second connector. The circuit translates a first data protocol transmitted by way of the first connector to a second data protocol transmitted by way of the second connector. The media holding device may further comprise a release member, wherein the release member is movable relative to the bay.
    Type: Application
    Filed: March 17, 2005
    Publication date: September 21, 2006
    Inventors: S. Sidle, Mike Erickson, Raymond Woodward
  • Patent number: 6918027
    Abstract: A system, such as a complex computer system, incorporates several programmable logic devices coupled to load their configuration code from associated EEPROMs; typically this load is automatic on powerup. The EEPROMs connect to one of several serial busses, typically JTAG busses, connecting the EEPROMs with a common configuration logic. A processor is configured to write programmable logic configuration code from its memory through the common configuration logic and over the serial busses into the EEPROMs. The processor is also capable of connecting to a network and fetching configuration code for writing to the EEPROMs.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: July 12, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paul Mantey, Mike Erickson, David Maciorowski
  • Publication number: 20040042034
    Abstract: A communications device for distributing an image of a paper document to a plurality of recipients having a database comprising a preferred electronic format of each of the recipients and an imaging device for converting the paper document into the preferred electronic format for each recipient in the database prior to distribution of the document in the preferred electronic format.
    Type: Application
    Filed: September 3, 2002
    Publication date: March 4, 2004
    Inventors: Jeff Tiffan, Jeff Wiley, Mike Erickson
  • Publication number: 20030020512
    Abstract: A system, such as a complex computer system, incorporates several programmable logic devices coupled to load their configuration code from associated EEPROMs; typically this load is automatic on powerup. The EEPROMs connect to one of several serial busses, typically JTAG busses, connecting the EEPROMs with a common configuration logic. A processor is configured to write programmable logic configuration code from its memory through the common configuration logic and over the serial busses into the EEPROMs. The processor is also capable of connecting to a network and fetching configuration code for writing to the EEPROMs.
    Type: Application
    Filed: July 30, 2001
    Publication date: January 30, 2003
    Inventors: Paul Mantey, Mike Erickson, David Maciorowski