Abstract: A remote monitoring system is provided including a sensor, for sensing data associated with a remotely monitored object; a transmitter coupled to the sensor, and for transmitting data of the sensor via satellite; and a notification system coupled to the transmitter, for receiving the sensor data and providing notifications to a user based upon the received sensor data.

Abstract: A remote monitoring system is provided including a sensor, for sensing data associated with a remotely monitored object; a transmitter coupled to the sensor, and for transmitting data of the sensor via satellite; and a notification system coupled to the transmitter, for receiving the sensor data and providing notifications to a user based upon the received sensor data.

Abstract: The present disclosure relates to systems and methods for analyzing chromosomal translocations, and in particular to analysis of chromosomal translocation by in situ hybridization.

Abstract: The present disclosure relates to systems and methods for analyzing chromosomal translocations, and in particular to analysis of chromosomal translocation by in situ hybridization.

Abstract: A delay-locked loop (DLL) circuit includes a phase interpolator circuit and variable delay circuit coupled in cascade and operative to generate an output clock signal that is delayed with respect to a reference clock signal responsive to respective first and second control signals applied to the phase interpolator and the variable delay circuit. The DLL circuit further includes a phase control circuit that generates the first and second control signals responsive to the output clock signal and the reference clock signal. The variable delay circuit may provide a coarser resolution than the phase interpolator circuit, for example, the variable delay circuit may include a tapped delay chain circuit configured to provide step changes in delay responsive to the second control signal.

Abstract: An integrated circuit memory device includes a memory, a read control circuit operatively associated with the memory and configured to produce data from the memory responsive to an externally-applied input clock signal, and an output latch configured to transfer data at an input thereof to an output pad of the memory device responsive to an externally-applied output clock signal. The device further includes a clock domain alignment circuit configured to receive the data produced by the memory and to responsively provide the data at the input of the output latch based on relative timing of the input clock signal and the output clock signal.