Patents by Inventor MIKE FILIPPO

MIKE FILIPPO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for optimizing prefetching of cache memory lines
    Patent number: 9063860
    Abstract: A method and system to optimize prefetching of cache memory lines in a processing unit. The processing unit has logic to determine whether a vector memory operand is cached in two or more adjacent cache memory lines. In one embodiment of the invention, the determination of whether the vector memory operand is cached in two or more adjacent cache memory lines is based on the size and the starting address of the vector memory operand. In one embodiment of the invention, the pre-fetching of the two or more adjacent cache memory lines that cache the vector memory operand is performed using a single instruction that uses one issue slot and one data cache memory execution slot. By doing so, it avoids additional software prefetching instructions or operations to read a single vector memory operand when the vector memory operand is cached in more than one cache memory line.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: June 23, 2015
    Assignee: Intel Corporation
    Inventors: Leigang Kou, Jeff Wiedemeier, Mike Filippo
  • METHOD AND SYSTEM FOR OPTIMIZING PREFETCHING OF CACHE MEMORY LINES
    Publication number: 20120254540
    Abstract: A method and system to optimize prefetching of cache memory lines in a processing unit. The processing unit has logic to determine whether a vector memory operand is cached in two or more adjacent cache memory lines. In one embodiment of the invention, the determination of whether the vector memory operand is cached in two or more adjacent cache memory lines is based on the size and the starting address of the vector memory operand. In one embodiment of the invention, the pre-fetching of the two or more adjacent cache memory lines that cache the vector memory operand is performed using a single instruction that uses one issue slot and one data cache memory execution slot. By doing so, it avoids additional software prefetching instructions or operations to read a single vector memory operand when the vector memory operand is cached in more than one cache memory line.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 4, 2012
    Inventors: LEIGANG KOU, JEFF WIEDEMEIER, MIKE FILIPPO