Patents by Inventor Mike H. Amidi
Mike H. Amidi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9424188Abstract: A method of operation of a non-volatile memory packaging system includes: addressing an integrated circuit package having a system interface; accessing a module controller, in the integrated circuit package, through system interface; accessing a random access memory, in the integrated circuit package, by the module controller for storing data from the system interface; writing to a non-volatile memory, in the integrated circuit package by the module controller, with the data from the random access memory; and monitoring an address look-up register, by the module controller, for reading the data from the non-volatile memory or the random access memory through the system interface.Type: GrantFiled: November 23, 2011Date of Patent: August 23, 2016Assignee: SMART Modular Technologies, Inc.Inventors: Mike H. Amidi, Michael Rubino, Alessandro Fin
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Patent number: 8767463Abstract: A method of operation of a non-volatile dynamic random access memory system including: accessing a dynamic random access memory; managing a delay-locked-loop control in the dynamic random access memory; sourcing timing inputs to the dynamic random access memory by a control logic unit with the delay-locked-loop control disabled including: selecting a back-up interface through a first multiplexer and a second multiplexer, asserting an on-board termination, and accessing data in the dynamic random access memory by the control logic unit at a lower frequency; and enabling a memory control interface by the control logic unit, with the delay-locked-loop control enabled including: selecting a host interface through the first multiplexer, the second multiplexer, or a combination thereof, disabling the on-board termination, and accessing the data in the dynamic random access memory by the memory control interface at a delay-locked-loop frequency.Type: GrantFiled: August 11, 2011Date of Patent: July 1, 2014Assignee: SMART Modular Technologies, Inc.Inventors: Mike H. Amidi, Kelvin Marino
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Patent number: 8644105Abstract: A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.Type: GrantFiled: April 29, 2010Date of Patent: February 4, 2014Assignee: SMART Modular Technologies, Inc.Inventors: Mike H. Amidi, Satyadev Kolli
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Publication number: 20130132639Abstract: A method of operation of a non-volatile memory packaging system includes: addressing an integrated circuit package having a system interface; accessing a module controller, in the integrated circuit package, through system interface; accessing a random access memory, in the integrated circuit package, by the module controller for storing data from the system interface; writing to a non-volatile memory, in the integrated circuit package by the module controller, with the data from the random access memory; and monitoring an address look-up register, by the module controller, for reading the data from the non-volatile memory or the random access memory through the system interface.Type: ApplicationFiled: November 23, 2011Publication date: May 23, 2013Applicant: SMART MODULAR TECHNOLOGIES, INC.Inventors: Mike H. Amidi, Michael Rubino, Alessandro Fin
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Patent number: 8423724Abstract: A method for operating a dynamic back-up storage system includes: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices; providing a non-volatile memory for saving data from the high speed memory; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device.Type: GrantFiled: September 8, 2010Date of Patent: April 16, 2013Assignee: SMART Modular Technologies, Inc.Inventors: Kelvin Marino, Michael Rubino, Mike H. Amidi
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Patent number: 8379391Abstract: A memory module with attached transposer and interposers to provide additional surface area for the placement of memory devices is disclosed. The memory module includes a memory board with a first surface, a second surface and an edge with a set of electrical contacts. A transposer is attached to each surface of the memory board, and an interposer is attached to each transposer on the opposite surface of the transposer from the memory board. The interposer has space to allow placement of memory devices on both a first surface between the interposer and the memory board, and on a second surface of the interposer away from the memory board.Type: GrantFiled: May 13, 2009Date of Patent: February 19, 2013Assignee: Smart Modular Technologies, Inc.Inventors: Mike H. Amidi, Robert S. Pauley, Satyanarayan Shivkumar Iyer
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Publication number: 20130039128Abstract: A method of operation of a non-volatile dynamic random access memory system including: accessing a dynamic random access memory; managing a delay-locked-loop control in the dynamic random access memory; sourcing timing inputs to the dynamic random access memory by a control logic unit with the delay-locked-loop control disabled including: selecting a back-up interface through a first multiplexer and a second multiplexer, asserting an on-board termination, and accessing data in the dynamic random access memory by the control logic unit at a lower frequency; and enabling a memory control interface by the control logic unit, with the delay-locked-loop control enabled including: selecting a host interface through the first multiplexer, the second multiplexer, or a combination thereof, disabling the on-board termination, and accessing the data in the dynamic random access memory by the memory control interface at a delay-locked-loop frequency.Type: ApplicationFiled: August 11, 2011Publication date: February 14, 2013Applicant: SMART MODULAR TECHNOLOGIES, INC.Inventors: Mike H. Amidi, Kelvin Marino
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Publication number: 20120060009Abstract: A method for operating a dynamic back-up storage system includes: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices; providing a non-volatile memory for saving data from the high speed memory; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device.Type: ApplicationFiled: September 8, 2010Publication date: March 8, 2012Applicant: SMART MODULAR TECHNOLOGIES, INC.Inventors: Kelvin Marino, Michael Rubino, Mike H. Amidi
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Patent number: 8068378Abstract: A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.Type: GrantFiled: April 29, 2010Date of Patent: November 29, 2011Assignee: Smart Modular Technologies, Inc.Inventors: Mike H. Amidi, Satyadev Kolli
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Patent number: 7937641Abstract: A memory module having error detection and correction mechanisms. The memory module includes a plurality of memory devices arranged in an array and a buffer device connected to the memory devices. The buffer device includes a register module for synchronizing and buffering a plurality of input signals to the memory devices, an error detection module for detecting errors of the input signals, and a transmission memory for storing a copy of the input signals and transmitting the stored copy of the input signals as an output signal. A buffer device for a memory module. A method of operating a memory module. A memory including a plurality of registers arranged in a pipeline for storing a plurality of copies of the input signals and communicating the stored copies of the input signals as an output signal to an external device.Type: GrantFiled: December 21, 2006Date of Patent: May 3, 2011Assignee: SMART Modular Technologies, Inc.Inventor: Mike H. Amidi
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Publication number: 20100238754Abstract: A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.Type: ApplicationFiled: April 29, 2010Publication date: September 23, 2010Applicant: SMART Modular Technologies, Inc.Inventors: Mike H. Amidi, Satyadev Kolli
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Publication number: 20100211765Abstract: A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.Type: ApplicationFiled: April 29, 2010Publication date: August 19, 2010Applicant: SMART Modular Technologies, Inc.Inventors: Mike H. Amidi, Satyadev Kolli
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Patent number: 7724604Abstract: A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.Type: GrantFiled: October 25, 2006Date of Patent: May 25, 2010Assignee: SMART Modular Technologies, Inc.Inventors: Mike H. Amidi, Satyadev Kolli
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Publication number: 20090279243Abstract: A memory module with attached transposer and interposers to provide additional surface area for the placement of memory devices is disclosed. The memory module includes a memory board with a first surface, a second surface and an edge with a set of electrical contacts. A transposer is attached to each surface of the memory board, and an interposer is attached to each transposer on the opposite surface of the transposer from the memory board. The interposer has space to allow placement of memory devices on both a first surface between the interposer and the memory board, and on a second surface of the interposer away from the memory board.Type: ApplicationFiled: May 13, 2009Publication date: November 12, 2009Inventors: Mike H. Amidi, Robert S. Pauley, Satyanarayan Shivkumar Iyer
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Patent number: 7509545Abstract: A method and system for testing memory modules is disclosed. The system includes a memory module and a connector configured to receive the module. The memory module is configured to operate in two modes: In the first operation mode the module uses a frequency between a low frequency and a high frequency. In the second operation mode, the module uses a frequency lower than the lower frequency. A control circuit is coupled to the connector. The control circuit is configured to apply a control signal to the circuit module when the circuit module is received in the connector. When the circuit module is received in the connector, the control signal is applied. This applied control signal causes the module to operate in the second operation mode.Type: GrantFiled: June 29, 2006Date of Patent: March 24, 2009Assignee: Smart Modular Technologies, Inc.Inventors: Mike H. Amidi, Michael Rubino, Larry C. Alchesky