Patents by Inventor Mike H. Cogdill

Mike H. Cogdill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods of selectively managing errors in memory modules
    Patent number: 8612797
    Abstract: System and methods of selectively managing errors in memory modules. In an exemplary implementation, a method may include monitoring for persistent errors in the memory modules. The methods may also include mapping at least a portion of the memory modules to a spare memory cache only to obviate persistent errors. The method may also include initiating memory erasure on at least a portion of the memory modules only if insufficient cache lines are available in the spare memory cache.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: December 17, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Larry J. Thayer, Andrew C. Walton, Mike H. Cogdill, George Krejci
  • System and method for implementing a stride value for memory testing
    Patent number: 7844868
    Abstract: Systems and methods for implementing a stride value for memory are provided. One embodiment relates to a system that includes a plurality of memory modules configured to store interleaved data in a plurality of memory storage units according to a predetermined interleave. A memory test device is configured to perform a memory test that accesses a portion of the plurality of memory storage units in a sequence according to a programmable stride value. The memory test device performs the memory test by writing test data to each of the memory storage units in the portion of the plurality of memory storage units and reading the test data from each of the memory storage units in the portion of the plurality of memory storage units.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: November 30, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Larry J. Thayer, Andrew C. Walton, Mike H. Cogdill
  • SYSTEM AND METHOD FOR IMPLEMENTING A STRIDE VALUE FOR MEMORY TESTING
    Publication number: 20100131810
    Abstract: Systems and methods for implementing a stride value for memory are provided. One embodiment relates to a system that includes a plurality of memory modules configured to store interleaved data in a plurality of memory storage units according to a predetermined interleave. A memory test device is configured to perform a memory test that accesses a portion of the plurality of memory storage units in a sequence according to a programmable stride value. The memory test device performs the memory test by writing test data to each of the memory storage units in the portion of the plurality of memory storage units and reading the test data from each of the memory storage units in the portion of the plurality of memory storage units.
    Type: Application
    Filed: January 27, 2010
    Publication date: May 27, 2010
    Inventors: LARRY J. THAYER, Andrew C. Walton, Mike H. Cogdill
  • Systems and methods for implementing a stride value for accessing memory
    Patent number: 7694193
    Abstract: Systems and methods for implementing a stride value for memory are provided. One embodiment includes a system comprising a plurality of memory modules configured to store interleaved data in a plurality of memory storage units according to a predetermined interleave. The plurality of memory storage units can be defined by a memory range of consecutive addresses. The system also comprises a memory test device configured to access a portion of the plurality of memory storage units in a sequence that repeats according to a programmable stride value.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: April 6, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Larry J. Thayer, Andrew C. Walton, Mike H. Cogdill
  • SYSTEMS AND METHODS FOR IMPLEMENTING A STRIDE VALUE FOR ACCESSING MEMORY
    Publication number: 20080229035
    Abstract: Systems and methods for implementing a stride valise for memory are provided. One embodiment includes a system comprising a plurality of memory modules configured to store interleaved data in a plurality of memory storage units according to a predetermined interleave. The plurality of memory storage units can be defined by a memory range of consecutive addresses. The system also comprises a memory test device configured to access a portion of the plurality of memory storage units in a sequence that repeats according to a programmable stride value.
    Type: Application
    Filed: March 13, 2007
    Publication date: September 18, 2008
    Inventors: Larry J. Thayer, Andrew C. Walton, Mike H. Cogdill