Abstract: Voltage sense circuit for measuring a load connected to a power amplifier, the load configured to receive a first and second voltage in opposite phase, the voltage sense circuit comprises a first input terminal coupled to the first voltage, a second input terminal coupled to the second voltage, a first voltage divider circuit comprising an input coupled to the first input terminal and an output coupled to the first output terminal, a second voltage divider circuit comprising an input coupled to the second input terminal and an output coupled to the second output terminal and a driver circuit comprising a first input configured to receive a reference voltage, a second input configured to receive a common mode signal of first and second voltage divider circuits, and an output to drive an output common mode voltage of the first and the second voltage divider circuits with the reference voltage.

Abstract: In one embodiment, a circuit-based apparatus that operates on an input data stream includes delay-line circuitry that characterizes the input data stream, modified over time. A plurality of integrators provide a plurality of integrated signals in response to the delay-line circuitry, and a plurality of weighting amplifiers amplify the plurality of integrated signals by a plurality of respective time-varying weighting factors to provide weighted signals. A signal-combining circuit combines the weighted signals. The circuit-based apparatus also includes a plurality of parallel signal-processing circuit paths that couple the weighted signals to the signal-combining circuit. By combining the weighted signals from the parallel signal-processing circuit paths, the signal-combining circuit provides a signal representative of the input data stream.

Abstract: In one embodiment, a circuit-based apparatus that operates on an input data stream includes delay-line circuitry that characterizes the input data stream, modified over time. A plurality of integrators provide a plurality of integrated signals in response to the delay-line circuitry, and a plurality of weighting amplifiers amplify the plurality of integrated signals by a plurality of respective time-varying weighting factors to provide weighted signals. A signal-combining circuit combines the weighted signals. The circuit-based apparatus also includes a plurality of parallel signal-processing circuit paths that couple the weighted signals to the signal-combining circuit. By combining the weighted signals from the parallel signal-processing circuit paths, the signal-combining circuit provides a signal representative of the input data stream.

Abstract: An electronic device with an amplifier output stage (OS) and an over-current detection means (OCDM) for detecting an output over-current (IHS, ILS) of the output stage (OS) is provided. The over-current detection means (OCDM) comprises a level detection means (LDM) for detecting a level of the output current (IO) exceeding a first level of the output current (IDET), and a timing detection means (TDM) for detecting a duration during which the output current (IO) exceeds the first current level (IDET) being a maximum current level.

Abstract: An electronic device with an amplifier output stage (OS) and an over-current detection means (OCDM) for detecting an output over-current (IHS, ILS) of the output stage (OS) is provided. The over-current detection means (OCDM) comprises a level detection means (LDM) for detecting a level of the output current (10) exceeding a first level of the output current (IDET), and a timing detection means (TDM) for detecting a duration during which the output current (10) exceeds the first current level (IDET) being a maximum current level.

Abstract: A driver circuit of an image display apparatus comprises driver circuit with a class A/B push-pull stage (T3, T5). The driver circuit contains an n-type pull transistor (T3), an n-type control transistor (T2) with a main current channel terminal coupled to a control electrode of the pull transistor (T2) and a voltage source (V) applying a predetermined voltage over a series connection of the control electrode-main current channel terminals of the control transistor (T2) and the pull transistor (T3). The current from the control transistor (T2) flows to a p-type push transistor (T5) via a current mirror (T4, T5). An input transistor (T1) draws all of the current from the control transistor (T2) via a node (142) between the control transistor (T2) and the pull transistor (T3) to control the ratio between the currents through these transistors (T2, T3).

Abstract: An electronic circuit comprising an amplifier includes an output terminal (OUT) for supplying an output signal (Vout) to a load, the amplifier comprising an output transistor (N2, P1) having a first main terminal coupled to a supply voltage terminal (VSS, VDD) of the amplifier, a second main terminal coupled to the output terminal (OUT), and a control terminal. In order to avoid that the output transistor (N2, P1) can enter its linear state which would cause the amplifier to act unacceptably slow for some purposes, the electronic circuit further comprises a controller adapted to prevent the output transistor (N2, P1) to enter its linear state whereby the controller is arranged for reducing a control voltage (Vcntrl) between the control terminal and the first main terminal when an output voltage (Vout) between the second main terminal and the first main terminal is below a defined level.

Abstract: An electronic circuit comprising an amplifier comprising an output terminal (OUT) for supplying an output signal (Vout) to a load, the amplifier comprising an output transistor (N2, P1) having a first main terminal coupled to a supply voltage terminal (Vss, VDD) of the amplifier, a second main terminal coupled to the output terminal (OUT), and a control terminal. In order to avoid that the output transistor (N2, P1) can enter its linear state which would cause the amplifier to act unacceptably slow for some purposes, the electronic circuit further comprises control means for avoiding the output transistor (N2, P1) to enter its linear state whereby the control means are arranged for reducing a control voltage (Vcntrl) between the control terminal and the first main terminal when an output voltage (Vout) between the second main terminal and the first main terminal is below a defined level.