Abstract: A method of storing data is provided. The method includes receiving commands from a system memory controller of a computer system. The commands include logical addresses and are received by a computer memory device comprising a parallel memory interface operatively coupled to the system memory controller and operatively coupled to a non-volatile memory. The method further includes responding to the commands by translating the received logical addresses to corresponding physical addresses of the non-volatile memory, receiving data from the system memory controller by the parallel memory interface, and storing the data at memory locations of the non-volatile memory corresponding to the physical addresses.

Abstract: A fast and lean way of performing logical-to-physical address translation is presented. A logical address is divided into a most significant bits portion and a least significant bits portion. Instead of using the entire logical address to locate an entry in an address translation table, only the most significant bits portion of the logical address is used, which substantially reduces the size of the address translation table. The entry includes a most significant bits portion of a physical volatile memory address and a most significant bits portion of a physical non-volatile memory address. The actual physical volatile memory address and the actual physical non-volatile memory address can be derived by combining the most significant bits portions of the addresses stored in the address translation table entry with the least significant bits portion of the logical address.

Abstract: A non-volatile memory system performs data operations efficiently for a host system by having a multi-layered architecture. The system includes multiple local controllers that are connected to an array of non-volatile memories, a master controller connected to the multiple local controllers, and an internal processing unit that communicates with the master controller. The internal processing unit receives data operation requests from the host system and generates groups of related operations. A group of related operations include a set of common addresses and multiple commands. The internal processing unit sends a group of related operations to the master controller, which in turn broadcasts the group of related operations to the local controllers, by first broadcasting addresses to the local controllers, broadcasting a first command to the local controllers, and then broadcasts a second command to the local controllers while the local controllers are still executing the first command.

Abstract: A system, method and apparatus to provide data recovery capabilities during an emergency power failure event. A non-volatile storage system is provided to be coupled with a host computer system. The non-volatile storage system includes an embedded non-volatile memory array for persistently storing data and an embedded volatile memory array for temporarily storing the data before committing the data to the non-volatile memory array. The non-volatile storage system provides a normal operating data path transferring data from the volatile memory array to the non-volatile memory array during normal operating condition. The normal operating data path includes data processing blocks. The non-volatile storage system also provides an emergency data path for transferring data from the volatile memory array to the non-volatile memory array during an emergency power loss condition. The emergency data path excludes the data processing blocks.

Abstract: An improved way of communicating data operation commands within a non-volatile storage controller is presented. The non-volatile storage controller includes an internal processing unit that is communicatively coupled with an associated host system, a master controller, and a plurality of local controllers that are communicatively coupled with a non-volatile memory. Upon receiving a series of data operations commands from the host system, the internal processing unit is configured to apply address shadowing when communicating the series of commands to the master controller such that the internal processing unit does not need to repetitively send the same set memory addresses to the master controller when issuing the series of commands.

Abstract: A system, method and apparatus to provide searching capabilities of a given queue to all of requested search patterns in a non-volatile storage unit with compressed data without decompression thereof. In one embodiment the invention provides system, method and apparatus to execute one or more queued search request of one or more search pattern for one or more non-volatile storage units without decompression of non-volatile storage units compressed data in sequence or in parallel, in order or out of order from the queue.

Abstract: A method of storing data is provided. The method includes receiving commands from a system memory controller of a computer system. The commands include logical addresses and are received by a computer memory device comprising a parallel memory interface operatively coupled to the system memory controller and operatively coupled to a non-volatile memory. The method further includes responding to the commands by translating the received logical addresses to corresponding physical addresses of the non-volatile memory, receiving data from the system memory controller by the parallel memory interface, and storing the data at memory locations of the non-volatile memory corresponding to the physical addresses.

Abstract: A computer memory device and a method of storing data are provided. The computer memory device includes a parallel memory interface configured to be operatively coupled to a system memory controller, to receive data and commands including logical addresses from the system memory controller, and to transmit data to the system memory controller. The parallel memory interface is configured to respond to the commands from the storage device driver of a computer processing unit. The computer memory device further includes an address translation circuit configured to receive the logical addresses from the parallel memory interface and to translate the received logical addresses to corresponding physical addresses. The computer memory device further includes a non-volatile memory operatively coupled to the parallel memory interface and the address translation circuit.

Abstract: A computer memory device and a method of storing data are provided. The computer memory device includes a parallel memory interface configured to be operatively coupled to a system memory controller, to receive data and commands including logical addresses from the system memory controller, and to transmit data to the system memory controller. The parallel memory interface is configured to respond to the commands from the storage device driver of a computer processing unit. The computer memory device further includes an address translation circuit configured to receive the logical addresses from the parallel memory interface and to translate the received logical addresses to corresponding physical addresses. The computer memory device further includes a non-volatile memory operatively coupled to the parallel memory interface and the address translation circuit.

Abstract: Data stored in a volatile memory subsystem is backed up redundantly into first and second channels of a non-volatile memory subsystem. The data is retrieved from the volatile memory subsystem upon detection of a trigger condition indicative of real or imminent power loss or reduction and multiple copies are stored in dedicated non-volatile memory channels. The stored copies may be error checked and corrected, and re-written if necessary. The redundantly backed up data can be subsequently retrieved from the non-volatile memory subsystem, error-corrected, and an error-free copy communicated to the volatile memory subsystem.

Abstract: Data stored in a volatile memory subsystem is backed up redundantly into first and second channels of a non-volatile memory subsystem. The data is retrieved from the volatile memory subsystem upon detection of a trigger condition indicative of real or imminent power loss or reduction and multiple copies are stored in dedicated non-volatile memory channels. The stored copies may be error checked and corrected, and re-written if necessary. The redundantly backed up data can be subsequently retrieved from the non-volatile memory subsystem, error-corrected, and an error-free copy communicated to the volatile memory subsystem.

Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.