Patents by Inventor Mike Jun

Mike Jun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Array test using the shorting bar and high frequency clock signal for the inspection of TFT-LCD with integrated driver IC
    Patent number: 7714589
    Abstract: In accordance with the present invention, a first shorting bar drives the data lines of a TFT array having integrated gate driver circuitry. Another set of shorting bars drive the corresponding terminals of the gate driver circuitry. The pixel voltages are measured after all the pixels are charged by the driving signals applied to the shorting bars. Gate voltages are progressively applied to the gate lines by the gate driver integrated circuit (IC) via the set of shorting bars that, in turn, are driven by clock signals received from one or more pattern generators. Voltages are concurrently applied to the data lines which are connected together by the first shorting bar. The application of voltages generates a display pattern that is subsequently compared to an expected display pattern. By comparing the resulting display pattern and the expected display pattern, possible defects are detected.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: May 11, 2010
    Assignee: Photon Dynamics, Inc.
    Inventors: Mike Jun, Atila Ersahin, Barry McGinley, Sabari Sanjeevi
  • Array Test Using The Shorting Bar And High Frequency Clock Signal For The Inspection Of TFT-LCD With Integrated Driver IC
    Publication number: 20070109011
    Abstract: In accordance with the present invention, a first shorting bar drives the data lines of a TFT array having integrated gate driver circuitry. Another set of shorting bars drive the corresponding terminals of the gate driver circuitry. The pixel voltages are measured after all the pixels are charged by the driving signals applied to the shorting bars. Gate voltages are progressively applied to the gate lines by the gate driver integrated circuit (IC) via the set of shorting bars that, in turn, are driven by clock signals received from one or more pattern generators. Voltages are concurrently applied to the data lines which are connected together by the first shorting bar. The application of voltages generates a display pattern that is subsequently compared to an expected display pattern. By comparing the resulting display pattern and the expected display pattern, possible defects are detected.
    Type: Application
    Filed: November 14, 2006
    Publication date: May 17, 2007
    Applicant: Photon Dynamics, Inc.
    Inventors: Mike Jun, Atila Ersahin, Barry McGinley, Sabari Sanjeevi