Patents by Inventor Mike Kavian Ranjram
Mike Kavian Ranjram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12051980Abstract: Described is a hybrid electronic and magnetic structure that enables a transformer with fractional and reconfigurable effective turns ratios (e.g. 12:0.5, 12:2/3, 12:1, and 12:2) and hereinafter referred to as a Variable-Inverter-Rectifier-Transformer (VIRT). A VIRT is valuable in converters having wide operating voltage ranges and high step-up/down, as it offers a means to reduce turns count and copper loss within a transformer while facilitating voltage doubling and quadrupling. Such characteristics are beneficial for reducing the size of a transformer stage in many power electronics applications, such as USB wall chargers. In embodiments, a VIRT comprises a plurality of switching cells distributed around a magnetic core and coupled to half-turns wound through that core. By controlling operating modes of the switching cells, it is possible to gain control over flux paths and current paths in the transformer.Type: GrantFiled: June 22, 2023Date of Patent: July 30, 2024Assignee: Massachusetts Institute of TechnologyInventors: David J. Perreault, Mike Kavian Ranjram, Intae Moon
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Publication number: 20230421069Abstract: Described is a hybrid electronic and magnetic structure that enables a transformer with fractional and reconfigurable effective turns ratios (e.g. 12:0.5, 12:2/3, 12:1, and 12:2) and hereinafter referred to as a Variable-Inverter-Rectifier-Transformer (VIRT). A VIRT is valuable in converters having wide operating voltage ranges and high step-up/down, as it offers a means to reduce turns count and copper loss within a transformer while facilitating voltage doubling and quadrupling. Such characteristics are beneficial for reducing the size of a transformer stage in many power electronics applications, such as USB wall chargers. In embodiments, a VIRT comprises a plurality of switching cells distributed around a magnetic core and coupled to half-turns wound through that core. By controlling operating modes of the switching cells, it is possible to gain control over flux paths and current paths in the transformer.Type: ApplicationFiled: June 22, 2023Publication date: December 28, 2023Applicant: Massachusetts Institute of TechnologyInventors: David J. Perreault, Mike Kavian Ranjram, Intae Moon
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Patent number: 11716030Abstract: Described is a hybrid electronic and magnetic structure that enables a transformer with fractional and reconfigurable effective turns ratios (e.g. 12:0.5, 12:?, 12:1, and 12:2) and hereinafter referred to as a Variable-Inverter-Rectifier-Transformer (VIRT). A VIRT is valuable in converters having wide operating voltage ranges and high step-up/down, as it offers a means to reduce turns count and copper loss within a transformer while facilitating voltage doubling and quadrupling. Such characteristics are beneficial for reducing the size of a transformer stage in many power electronics applications, such as USB wall chargers. In embodiments, a VIRT comprises a plurality of switching cells distributed around a magnetic core and coupled to half-turns wound through that core. By controlling operating modes of the switching cells, it is possible to gain control over flux paths and current paths in the transformer.Type: GrantFiled: March 2, 2018Date of Patent: August 1, 2023Assignee: Massachusetts Institute of TechnologyInventors: David J. Perreault, Mike Kavian Ranjram, Intae Moon
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Patent number: 11289906Abstract: A module for interconnecting a pair of DC sources or a pair of DC loads into a DC bus includes: a first port for each source or load; a switching cell for each first port, each cell having a pair of terminals and a switching node; a second port operatively connected to the DC bus and having a pair of terminals, one of the pair of terminals of the second port being connected to one of the terminals of one of the cells and the other of the pair of terminals of the second port being connected to one of the terminals of the other of the cells; and a filter inductor connected between the switching nodes of the cells. Systems including the module and methods utilizing the system are also disclosed.Type: GrantFiled: August 15, 2020Date of Patent: March 29, 2022Assignee: THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTOInventors: Peter Waldemar Lehn, Mike Kavian Ranjram, Sebastian Rivera Iunnissi, Yuanzheng Han
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Publication number: 20210036515Abstract: A module for interconnecting a pair of DC sources or a pair of DC loads into a DC bus includes: a first port for each source or load; a switching cell for each first port, each cell having a pair of terminals and a switching node; a second port operatively connected to the DC bus and having a pair of terminals, one of the pair of terminals of the second port being connected to one of the terminals of one of the cells and the other of the pair of terminals of the second port being connected to one of the terminals of the other of the cells; and a filter inductor connected between the switching nodes of the cells. Systems including the module and methods utilizing the system are also disclosed.Type: ApplicationFiled: August 15, 2020Publication date: February 4, 2021Inventors: Peter Waldemar LEHN, Mike Kavian RANJRAM, Sebastian Rivera IUNNISSI, Yuanzheng HAN
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Patent number: 10770893Abstract: A module for interconnecting a pair of DC sources or a pair of DC loads into a DC bus includes: a first port for each source or load; a switching cell for each first port, each cell having a pair of terminals and a switching node; a second port operatively connected to the DC bus and having a pair of terminals, one of the pair of terminals of the second port being connected to one of the terminals of one of the cells and the other of the pair of terminals of the second port being connected to one of the terminals of the other of the cells; and a filter inductor connected between the switching nodes of the cells. Systems including the module and methods utilizing the system are also disclosed.Type: GrantFiled: October 20, 2017Date of Patent: September 8, 2020Assignee: THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTOInventors: Peter Waldemar Lehn, Mike Kavian Ranjram, Sebastian Rivera Iunnissi, Yuanzheng Han
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Publication number: 20190229633Abstract: Described is a hybrid electronic and magnetic structure that enables a transformer with fractional and reconfigurable effective turns ratios (e.g. 12:0.5, 12:?, 12:1, and 12:2) and hereinafter referred to as a Variable-Inverter-Rectifier-Transformer (VIRT). A VIRT is valuable in converters having wide operating voltage ranges and high step-up/down, as it offers a means to reduce turns count and copper loss within a transformer while facilitating voltage doubling and quadrupling. Such characteristics are beneficial for reducing the size of a transformer stage in many power electronics applications, such as USB wall chargers. In embodiments, a VIRT comprises a plurality of switching cells distributed around a magnetic core and coupled to half-turns wound through that core. By controlling operating modes of the switching cells, it is possible to gain control over flux paths and current paths in the transformer.Type: ApplicationFiled: March 2, 2018Publication date: July 25, 2019Inventors: David J. PERREAULT, Mike Kavian RANJRAM, Intae MOON
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Patent number: 10291123Abstract: A module for interconnecting a pair of DC sources or a pair of DC loads into a DC bus includes: a first port for each source or load; a switching cell for each first port, each cell having a pair of terminals and a switching node; a second port operatively connected to the DC bus and having a pair of terminals, one of the pair of terminals of the second port being connected to one of the terminals of one of the cells and the other of the pair of terminals of the second port being connected to one of the terminals of the other of the cells; and a filter inductor connected between the switching nodes of the cells. Systems including the module and methods utilizing the system are also disclosed.Type: GrantFiled: April 30, 2015Date of Patent: May 14, 2019Assignee: THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTOInventors: Peter Waldemar Lehn, Mike Kavian Ranjram, Yuanzheng Han
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Publication number: 20180123341Abstract: A module for interconnecting a pair of DC sources or a pair of DC loads into a DC bus includes: a first port for each source or load; a switching cell for each first port, each cell having a pair of terminals and a switching node; a second port operatively connected to the DC bus and having a pair of terminals, one of the pair of terminals of the second port being connected to one of the terminals of one of the cells and the other of the pair of terminals of the second port being connected to one of the terminals of the other of the cells; and a filter inductor connected between the switching nodes of the cells. Systems including the module and methods utilizing the system are also disclosed.Type: ApplicationFiled: October 20, 2017Publication date: May 3, 2018Inventors: Peter Waldemar LEHN, Mike Kavian RANJRAM, Sebastian Rivera IUNNISSI, Yuanzheng HAN
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Publication number: 20170063233Abstract: A module for interconnecting a pair of DC sources or a pair of DC loads into a DC bus includes: a first port for each source or load; a switching cell for each first port, each cell having a pair of terminals and a switching node; a second port operatively connected to the DC bus and having a pair of terminals, one of the pair of terminals of the second port being connected to one of the terminals of one of the cells and the other of the pair of terminals of the second port being connected to one of the terminals of the other of the cells; and a filter inductor connected between the switching nodes of the cells. Systems including the module and methods utilizing the system are also disclosed.Type: ApplicationFiled: April 30, 2015Publication date: March 2, 2017Inventors: Peter Waldemar Lehn, Mike Kavian Ranjram, Yuanzheng Han