Abstract: A computer system to compress bit formats provided in a first packed data sequence. The computer system include a processor, a multimedia input device to receive an image or audio input, a memory having stored thereon a set of packed data sequences having data elements representing the input, and a compression routine for manipulating the input. When the compression routine is executed by the processor, the routine causes the processor to: generate a second packed data sequence by copying the first packed data sequence; mask a portion of the first packed data sequence; shift data elements of the first packed data sequence, in response to executing a single first instruction, wherein the data elements are independently shifted by separate shift counts; mask a portion of the second packed data sequence; and generate a final result by joining the second and first packed data sequences.

Abstract: A computer implemented method for compressing bit formats provided in a first packed data sequence. One embodiment of the method comprises the steps of generating, in response to executing a first instruction, a second packed data sequence by copying the first packed data sequence. A second step of masking, in response to executing a second instruction, a portion of the first packed data sequence. A third step of shifting data elements of the first packed data sequence, in response to executing a third instruction, wherein the data elements are independently shifted by separate shift counts. A fourth step of masking, in response to executing a fourth instruction, a portion of the second packed data sequence. A fifth step of generating, in response to executing a fifth instruction, a final result by joining the second and first packed data sequences.

Abstract: A computer implemented method for compressing bit formats provided in a first packed data sequence. One embodiment of the method comprises the steps of generating, in response to executing a first instruction, a second packed data sequence by copying the first packed data sequence. A second step of masking, in response to executing a second instruction, a portion of the first packed data sequence. A third step of shifting data elements of the first packed data sequence, in response to executing a third instruction, wherein the data elements are independently shifted by separate shift counts. A fourth step of masking, in response to executing a fourth instruction, a portion of the second packed data sequence. A fifth step of generating, in response to executing a fifth instruction, a final result by joining the second and first packed data sequences.

Abstract: Data is exchanged between two modules of a programmable controller by originator module writing the information in an interface memory in one of the modules and the recipient module reading the information from the memory. An initialization procedure is performed before any information is exchanged in that manner. The module containing the memory writes the size of the memory for reading by the other module. Sets of test data are stored in the memory by each module and checked by the other module to determine if data can be passed accurately between the modules in both directions. Then data identifying the type of one of the modules is exchanged to insure that the other module knows the type of module with which it is dealing.