Abstract: A PLL system (10) includes a PFD (24) that receives a reference clock signal (REF CLK) and a feedback clock signal (FBK CLK). The PFD (24) generates an analog signal (TUNE) based on the phase and frequency relationship of the reference and feedback clock signals. The PFD (24) also generates a clock signal based on two PI phase slips for clocking a counter (70). The analog signal is compared against an upper and lower reference voltage in a threshold detect circuit (34) and the signals UP and DOWN supplied to the counter (70). The counter (70) provides a count value that controls the resonant frequency generated by a tank circuit (73). The tuning range of an oscillator (18) is extended by changing the capacitance of the tank circuit (73).