Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract: Hemagglutination (HA) and hemagglutination inhibition (HAI) functional assays remain important instruments of analysis of virus-cell interaction and protecting efficacy of virus-specific antibodies and sera. However, they demonstrate limited sensitivity towards many viruses, and require significant volumes of viruses, erythrocytes, sera, and antibodies. The present invention comprises new and significantly more sensitive versions of the HA and HAI assays based on observing agglutination on activated surfaces of specifically opsonized plates and ELISA plates rather than in solution. A version of the new assay that uses ELISA plates additionally allows characterizing the affinity of functional antibodies in the tested sera and fluids, which is not possible in the classical HAI assay. The methods of the present invention can also be used to improve the sensitivity of agglutination methods based on latex beads and to develop agglutination methods using target cells other than erythrocytes.

Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract: Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract: Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract: Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract: Hemagglutination (HA) and hemagglutination inhibition (HAI) functional assays remain important instruments of analysis of virus-cell interaction and protecting efficacy of virus-specific antibodies and sera. However, they demonstrate limited sensitivity towards many viruses, and require significant volumes of viruses, erythrocytes, sera, and antibodies. The present invention comprises new and significantly more sensitive versions of the HA and HAI assays based on observing agglutination on activated surfaces of specifically opsonized plates and ELISA plates rather than in solution. A version of the new assay that uses ELISA plates additionally allows characterizing the affinity of functional antibodies in the tested sera and fluids, which is not possible in the classical HAI assay. The methods of the present invention can also be used to improve the sensitivity of agglutination methods based on latex beads and to develop agglutination methods using target cells other than erythrocytes.

Abstract: Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer and including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage and extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell includes a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.