Patents by Inventor Mike Nakahara
Mike Nakahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240356635Abstract: Examples are disclosed that relate to improving security of radio frequency (RF) backscattered communication. In one example, a RF device includes a primary RF signal receiver, a secondary signal receiver, a signal mixer, and a transmitter. The primary RF signal receiver is configured to receive a RF carrier signal sent from a base station. The secondary signal receiver is configured to receive a masking signal from the base station. The signal mixer is configured to generate a response signal based at least on the RF carrier signal and generate a mixed signal by mixing the response signal and the masking signal. The transmitter is configured to broadcast the mixed signal, via backscattering, as a masked backscattered signal.Type: ApplicationFiled: April 19, 2023Publication date: October 24, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Vaishnavi NATTAR RANGANATHAN, Nissanka Arachchige Bodhi PRIYANTHA, Mike NAKAHARA, Vikram Subramaniam IYER, Harsh Sandesh DESAI
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Publication number: 20230276104Abstract: An audio/video (AV) receiver is adapted to be dynamically reconfigured in a selected one of an encrypted content support mode and an unencrypted content support mode. The AV receiver includes a controller configured to dynamically alter one or more encryption settings based at least in part on user input provided to a mode toggle mechanism. The one or more altered encryption settings are effective to facilitate presentation of unencrypted content within a received media stream on a display while selectively preventing presentation of encrypted content included in the received media stream on the display.Type: ApplicationFiled: May 9, 2023Publication date: August 31, 2023Inventors: Ashif NAZIRUDEEN, Mike NAKAHARA, Allan Christopher ECKER
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Patent number: 11689774Abstract: An audio/video (AV) receiver is adapted to be dynamically reconfigured in a selected one of an encrypted content support mode and an unencrypted content support mode. The AV receiver includes a controller configured to dynamically alter one or more encryption settings based at least in part on user input provided to a mode toggle mechanism. The one or more altered encryption settings are effective to facilitate presentation of unencrypted content within a received media stream on a display while selectively preventing presentation of encrypted content included in the received media stream on the display.Type: GrantFiled: April 20, 2021Date of Patent: June 27, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Ashif Nazirudeen, Mike Nakahara, Allan Christopher Ecker
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Publication number: 20220224987Abstract: An audio/video (AV) receiver is adapted to be dynamically reconfigured in a selected one of an encrypted content support mode and an unencrypted content support mode. The AV receiver includes a controller configured to dynamically alter one or more encryption settings based at least in part on user input provided to a mode toggle mechanism. The one or more altered encryption settings are effective to facilitate presentation of unencrypted content within a received media stream on a display while selectively preventing presentation of encrypted content included in the received media stream on the display.Type: ApplicationFiled: April 20, 2021Publication date: July 14, 2022Inventors: Ashif NAZIRUDEEN, Mike NAKAHARA, Allan Christopher ECKER
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Patent number: 9681422Abstract: A method of operating a transceiver may comprise operating in an adaptive mode in which transmissions from the transceiver are halted after detection of interference, performing a clear channel assessment (CCA), as a result of the CCA, detecting energy from an interferer above a predetermined threshold, and switching operation to a non-adaptive mode in which the transceiver is configured to alternate transmission periods and idle periods according to a duty cycle. Then, the method may comprise performing an energy detect, as a result of the energy detect, subsequently detecting the energy from the interferer below the predetermined threshold, and switching operation to the adaptive mode.Type: GrantFiled: April 21, 2015Date of Patent: June 13, 2017Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Mike Nakahara, Stanley William Adermann
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Patent number: 9553640Abstract: Methods and devices for use with a multi-feed antenna used in a MIMO communication system are described herein. A method can include obtaining an antenna feed characteristic indicator associated with each of the feeds of the multi-feed antenna, and controlling how power is distributed among the feeds based on the antenna feed characteristic indicator associated with each of the feeds. An antenna feed characteristic indicator can be, e.g., an indicator of impedance matching, in which case power can be distributed among the feeds of the multi-feed antenna based on the indicators of impedance matching associate with each of the feeds. Power can also be distributed based on an indicator of link quality. Additionally, or alternatively, coding rate and/or modulation type can also be controlled for each of the feeds of the multi-feed antenna, based on one or more antenna feed characteristic indicators and/or one or more indicators of link quality.Type: GrantFiled: December 22, 2015Date of Patent: January 24, 2017Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Ranveer Chandra, Lopamudra Kundu, Mike Nakahara, Srihari Narlanka, Gerald DeJean
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Publication number: 20160192328Abstract: A method of operating a transceiver may comprise operating in an adaptive mode in which transmissions from the transceiver are halted after detection of interference, performing a clear channel assessment (CCA), as a result of the CCA, detecting energy from an interferer above a predetermined threshold, and switching operation to a non-adaptive mode in which the transceiver is configured to alternate transmission periods and idle periods according to a duty cycle. Then, the method may comprise performing an energy detect, as a result of the energy detect, subsequently detecting the energy from the interferer below the predetermined threshold, and switching operation to the adaptive mode.Type: ApplicationFiled: April 21, 2015Publication date: June 30, 2016Inventors: Mike Nakahara, Stanley William Adermann
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Patent number: 6008823Abstract: The present invention is directed to providing an organized memory which is accessed by multiple memory controllers while still exploiting the efficiencies which the organized memory was intended to provide. In accordance with exemplary embodiments, optimal efficiency in using the shared memory is achieved by buffering memory accesses which will not increase overhead during a memory write cycle. As a result, interruptions by one controller while another controller is accessing the shared memory are reduced to a minimum.Type: GrantFiled: August 1, 1995Date of Patent: December 28, 1999Inventors: Desi Rhoden, Judson Alan Lehman, Mike Nakahara
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Patent number: 5659715Abstract: A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory is selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. A reallocatable memory subsystem enables transparent transfer of memory function of a lower-performance memory such as DRAM to occur in conjunction with a memory upgrade to a higher-performance memory such as VRAM, for example.Type: GrantFiled: May 8, 1996Date of Patent: August 19, 1997Assignee: VLSI Technology, Inc.Inventors: Shih-Ho Wu, William Desi Rhoden, Mike Nakahara
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Patent number: 5559533Abstract: A hardware cursor is implemented on a typical video display controller, and uses an unused portion of video RAM as cursor memory to store the cursor information. Since the cursor memory may be located at any unused location of video RAM, it is a virtual hardware cursor since the location of cursor data may changed as required. The operation of the cursor may be programmed, monitored and controlled via control registers. The hardware cursor monitors the video control signals to determine when to put out cursor data rather than directly outputting pixel data. The hardware cursor fetches the appropriate cursor data from the cursor memory in the video RAM during the horizontal nondisplay period just prior to a line of display data that should contain cursor data. The hardware cursor then monitors the pixel stream and outputs unchanged pixel data until a cursor location is reached, at which time the hardware cursor outputs a logical combination of cursor data, cursor color, and pixel value.Type: GrantFiled: September 30, 1994Date of Patent: September 24, 1996Assignee: VLSI Technology, Inc.Inventors: Gary D. Hicok, Dale C. Penner, Mike Nakahara
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Patent number: 5454107Abstract: A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. Efficient L2 cache memory support is provided based on a system controller having an integrated L2 cache controller and a graphics controller that supports an integrated memory system. The memory connected to the graphics controller may be partitioned into two sections, one for graphics and one for system use. Additionally, the system controller may or may not have attached additional memory for system use. L2 cache support is provided for all system memory, regardless of the controller that it is connected to.Type: GrantFiled: November 30, 1993Date of Patent: September 26, 1995Assignee: VLSI TechnologiesInventors: Judson A. Lehman, Mike Nakahara, Nicholas J. Richardson