Abstract: An audio/video (AV) receiver is adapted to be dynamically reconfigured in a selected one of an encrypted content support mode and an unencrypted content support mode. The AV receiver includes a controller configured to dynamically alter one or more encryption settings based at least in part on user input provided to a mode toggle mechanism. The one or more altered encryption settings are effective to facilitate presentation of unencrypted content within a received media stream on a display while selectively preventing presentation of encrypted content included in the received media stream on the display.

Abstract: An audio/video (AV) receiver is adapted to be dynamically reconfigured in a selected one of an encrypted content support mode and an unencrypted content support mode. The AV receiver includes a controller configured to dynamically alter one or more encryption settings based at least in part on user input provided to a mode toggle mechanism. The one or more altered encryption settings are effective to facilitate presentation of unencrypted content within a received media stream on a display while selectively preventing presentation of encrypted content included in the received media stream on the display.

Abstract: An audio/video (AV) receiver is adapted to be dynamically reconfigured in a selected one of an encrypted content support mode and an unencrypted content support mode. The AV receiver includes a controller configured to dynamically alter one or more encryption settings based at least in part on user input provided to a mode toggle mechanism. The one or more altered encryption settings are effective to facilitate presentation of unencrypted content within a received media stream on a display while selectively preventing presentation of encrypted content included in the received media stream on the display.

Abstract: A method of operating a transceiver may comprise operating in an adaptive mode in which transmissions from the transceiver are halted after detection of interference, performing a clear channel assessment (CCA), as a result of the CCA, detecting energy from an interferer above a predetermined threshold, and switching operation to a non-adaptive mode in which the transceiver is configured to alternate transmission periods and idle periods according to a duty cycle. Then, the method may comprise performing an energy detect, as a result of the energy detect, subsequently detecting the energy from the interferer below the predetermined threshold, and switching operation to the adaptive mode.

Abstract: Methods and devices for use with a multi-feed antenna used in a MIMO communication system are described herein. A method can include obtaining an antenna feed characteristic indicator associated with each of the feeds of the multi-feed antenna, and controlling how power is distributed among the feeds based on the antenna feed characteristic indicator associated with each of the feeds. An antenna feed characteristic indicator can be, e.g., an indicator of impedance matching, in which case power can be distributed among the feeds of the multi-feed antenna based on the indicators of impedance matching associate with each of the feeds. Power can also be distributed based on an indicator of link quality. Additionally, or alternatively, coding rate and/or modulation type can also be controlled for each of the feeds of the multi-feed antenna, based on one or more antenna feed characteristic indicators and/or one or more indicators of link quality.

Abstract: A method of operating a transceiver may comprise operating in an adaptive mode in which transmissions from the transceiver are halted after detection of interference, performing a clear channel assessment (CCA), as a result of the CCA, detecting energy from an interferer above a predetermined threshold, and switching operation to a non-adaptive mode in which the transceiver is configured to alternate transmission periods and idle periods according to a duty cycle. Then, the method may comprise performing an energy detect, as a result of the energy detect, subsequently detecting the energy from the interferer below the predetermined threshold, and switching operation to the adaptive mode.

Abstract: The present invention is directed to providing an organized memory which is accessed by multiple memory controllers while still exploiting the efficiencies which the organized memory was intended to provide. In accordance with exemplary embodiments, optimal efficiency in using the shared memory is achieved by buffering memory accesses which will not increase overhead during a memory write cycle. As a result, interruptions by one controller while another controller is accessing the shared memory are reduced to a minimum.

Abstract: A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory is selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. A reallocatable memory subsystem enables transparent transfer of memory function of a lower-performance memory such as DRAM to occur in conjunction with a memory upgrade to a higher-performance memory such as VRAM, for example.

Abstract: A hardware cursor is implemented on a typical video display controller, and uses an unused portion of video RAM as cursor memory to store the cursor information. Since the cursor memory may be located at any unused location of video RAM, it is a virtual hardware cursor since the location of cursor data may changed as required. The operation of the cursor may be programmed, monitored and controlled via control registers. The hardware cursor monitors the video control signals to determine when to put out cursor data rather than directly outputting pixel data. The hardware cursor fetches the appropriate cursor data from the cursor memory in the video RAM during the horizontal nondisplay period just prior to a line of display data that should contain cursor data. The hardware cursor then monitors the pixel stream and outputs unchanged pixel data until a cursor location is reached, at which time the hardware cursor outputs a logical combination of cursor data, cursor color, and pixel value.

Abstract: A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. Efficient L2 cache memory support is provided based on a system controller having an integrated L2 cache controller and a graphics controller that supports an integrated memory system. The memory connected to the graphics controller may be partitioned into two sections, one for graphics and one for system use. Additionally, the system controller may or may not have attached additional memory for system use. L2 cache support is provided for all system memory, regardless of the controller that it is connected to.