Abstract: In the described examples, an electronic design automation formal verification EDA application is configured to receive an initial evaluation of a circuit design of an integrated circuit (IC) chip. The circuit design of the IC chip includes a list of properties for the IC chip, and the list of properties includes a list of assertions for the IC chip. The formal verification EDA program extracts a counter-example trace from the initial evaluation. The counter-example trace characterizes a set of signals over a plurality of cycles that reach a state in which a given assertion in the list of assertions does not hold true. The formal verification EDA program identifies a subset of signals in the counter-example trace that remain in a specific constant value over the plurality of cycles. The formal verification EDA program executes an over-constrained formal verification for the circuit design.

Abstract: A microprocessor is configured to speculatively fetch cache lines of instruction bytes prior to actually detecting a cache miss for the cache lines of instruction bytes. The bytes transferred from an external main memory subsystem are stored into one of several prefetch buffers. Subsequently, instruction fetches may be detected which hit the prefetch buffers. Furthermore, predecode data may be generated for the instruction bytes stored in the prefetch buffers. When a fetch hit in the prefetch buffers is detected, predecode data may be available for the instructions being fetched. The prefetch buffers may each comprise an address prefetch buffer included within an external interface unit and an instruction data prefetch buffer included within a prefetch/predecode unit. The external interface unit maintains the addresses of cache lines assigned to the prefetch buffers in the address prefetch buffers. Both the linear address and the physical address of each cache line is maintained.