Abstract: A method of saving/restoring a processor state after entering/exiting a debug mode. When a processor desires to perform a debugging process, the processor enters a debug mode. A resume instruction is produced. The program counter of the resume instruction is stored into a register. The debugging instructions are performed without need to count the number of the instructions having been executed during the debug mode. When the processor wants to exit the debug mode, then the processor fetches the program counter stored in the register, and jumps back to the resume instruction.

Abstract: The invention is directed to a method for fetching at least one word instruction in a word-based processor. The word instruction includes several types of a full-word instruction or a half-word instruction. The processor employs a data bus with a word length in bit. The method includes dividing the word length into a plurality of world units by 2n bits. The processor checks the memory request to obtain whether or not the word instruction to be fetched is in a sequential half-word aligned address. If it is, then the processor fetches the sequential multiple half-word instructions at the same time in full word length at a first fetch cycle. The half-word instructions are stored in the word units. Then, the half-word instructions are executed without directly fetching the half-word instructions from the memory in each the fetch cycles. A circuit is also provided to fetch the word instruction.