Abstract: A method implemented by a processor and a system develop a software project targeting one or more remote systems. The method includes generating a project on a local system, which includes receiving user input through a user interface. The project includes one or more source files. The method also includes generating one or more remote contexts corresponding to the one or more remote systems.

Abstract: A computer-implemented process for creating a packed data object, the computer-implemented process comprising providing instrumentation to an enhanced runtime by an enhanced compiler for a computer executable program portion, detecting a special class in the computer executable program portion by the enhanced runtime, creating an internal representation of a packed data object header using the instrumentation, calculating a size of elements for a packed data object associated with the computer executable program portion, determining a type of packed data object using information in the packed data object header, and responsive to a determination that the type of packed data object is an on-heap packed data object, storing the packed data object header and associated packed data object data together for the packed data object in a memory heap.

Abstract: Embodiments of the present invention provide a method, system and computer program product for dynamic feasibility analysis of event-driven program code. In an embodiment of the invention, a method for a dynamic feasibility analysis of event-driven program code can be provided.

Abstract: A method implemented by a processor and a system develop a software project targeting one or more remote systems. The method includes generating a project on a local system, which includes receiving user input through a user interface. The project includes one or more source files. The method also includes generating one or more remote contexts corresponding to the one or more remote systems.

Abstract: A method, computer program product, and data processing system for substituting a candidate instruction in application code being loaded during load time. Responsive to identifying the candidate instruction, a determination is made whether a hardware facility of the data processing system is present to execute the candidate instruction. If the hardware facility is absent from the data processing system, the candidate instruction is substituted with a second set of instructions.

Abstract: A computer-implemented process for creating a packed data object, the computer-implemented process comprising providing instrumentation to an enhanced runtime by an enhanced compiler for a computer executable program portion, detecting a special class in the computer executable program portion by the enhanced runtime, creating an internal representation of a packed data object header using the instrumentation, calculating a size of elements for a packed data object associated with the computer executable program portion, determining a type of packed data object using information in the packed data object header, and responsive to a determination that the type of packed data object is an on-heap packed data object, storing the packed data object header and associated packed data object data together for the packed data object in a memory heap.

Abstract: A method, article, and system for providing an effective implementation of assembler language translate-n-to-n instructions implemented on 21, 31, and 64-bit architectures, while maintaining backward compatibility with existing systems. The enhanced Extended-Translation Facility 2 (ETF2) instruction set introduces a new operand in an unused field (M3) that facilitates a change in the original instruction format and its intended function. With the ETF2-Enhancement Facility installed, a value of zeros in the M3 field indicates that instruction operation is to continue as originally defined. When a nonzero value is coded in the M3 field a new function is carried out. The assembler accommodates the changes by making the new M3 field optional when coding the instructions. If the M3 field is not coded, the assembler defaults to providing zeros in the M3 field (as found in the original instruction format), and backward compatible operation is provided.

Abstract: An illustrative embodiment of a computer-implemented process for delegating access to private data receives a request at a trusted server, forwards the received request to an untrusted third party application and invokes a transaction on a secure data store. The computer-implemented process further tokenizes data received from the secure data store by the trusted server, returns the tokenized data to the untrusted third party application, modifies the tokenized data by the untrusted third party application, requests the trusted server to send results to a requester and sends the results from the trusted server to the requester for display.

Abstract: A method, article, and system for providing an effective implementation of assembler language translate-n-to-n instructions implemented on 21, 31, and 64-bit architectures, while maintaining backward compatibility with existing systems. The enhanced Extended-Translation Facility 2 (ETF2) instruction set introduces a new operand in an unused field (M3) that facilitates a change in the original instruction format and its intended function. With the ETF2-Enhancement Facility installed, a value of zeros in the M3 field indicates that instruction operation is to continue as originally defined. When a nonzero value is coded in the M3 field a new function is carried out. The assembler accommodates the changes by making the new M3 field optional when coding the instructions. If the M3 field is not coded, the assembler defaults to providing zeros in the M3 field (as found in the original instruction format), and backward compatible operation is provided.

Abstract: A method, article, and system for providing an effective implementation of assembler language translate-n-to-n instructions implemented on 21, 31, and 64-bit architectures, while maintaining backward compatibility with existing systems. The enhanced Extended-Translation Facility 2 (ETF2) instruction set introduces a new operand in an unused field (M3) that facilitates a change in the original instruction format and its intended function. With the ETF2-Enhancement Facility installed, a value of zeros in the M3 field indicates that instruction operation is to continue as originally defined. When a nonzero value is coded in the M3 field a new function is carried out. The assembler accommodates the changes by making the new M3 field optional when coding the instructions. If the M3 field is not coded, the assembler defaults to providing zeros in the M3 field (as found in the original instruction format), and backward compatible operation is provided.

Abstract: A method is provided for recording a list of facilities available to a program executing on an information processing system. In such method a storage location and a length of data are defined for recording the list of facilities by a program being executed on the information processing system. An instruction is issued by the program for determining the available facilities and recording the list of available facilities in accordance with the defined storage location and data length. A processor executes the instruction to determine the available facilities and record the list of facilities in accordance with the defined storage location and defined data length. The recorded list of facilities can then be read by the first program.

Abstract: A register-based instruction optimization is provided for facilitating efficient emulation of a target instruction stream. The optimization includes for at least one instruction in a frequently executed sequence of target instructions: confirming that at least one register is marked as a read-only register for the sequence; confirming that each register of the at least one register has been detected to have a constant value for the at least one instruction in multiple prior iterations of the executed sequence; and response thereto, optimizing the at least one instruction by replacing the at least one instruction with at least one immediate form instruction having at least one constant value encoded directly therein from the at least one register. The optimization results in an optimized sequence of target instructions, which when translated into a sequence of host instructions, is more efficiently executed by a host computing environment.

Abstract: Embodiments of the present invention provide a method, system and computer program product for dynamic feasibility analysis of event-driven program code. In an embodiment of the invention, a method for a dynamic feasibility analysis of event-driven program code can be provided.

Abstract: A method, article, and system for providing an effective implementation of assembler language translate-n-to-n instructions implemented on 21, 31, and 64-bit architectures, while maintaining backward compatibility with existing systems. The enhanced Extended-Translation Facility 2 (ETF2) instruction set introduces a new operand in an unused field (M3) that facilitates a change in the original instruction format and its intended function. With the ETF2-Enhancement Facility installed, a value of zeros in the M3 field indicates that instruction operation is to continue as originally defined. When a nonzero value is coded in the M3 field a new function is carried out. The assembler accommodates the changes by making the new M3 field optional when coding the instructions. If the M3 field is not coded, the assembler defaults to providing zeros in the M3 field (as found in the original instruction format), and backward compatible operation is provided.

Abstract: A register-based instruction optimization is provided for facilitating efficient emulation of a target instruction stream. The optimization includes for at least one instruction in a frequently executed sequence of target instructions: confirming that at least one register is marked as a read-only register for the sequence; confirming that each register of the at least one register has been detected to have a constant value for the at least one instruction in multiple prior iterations of the executed sequence; and response thereto, optimizing the at least one instruction by replacing the at least one instruction with at least one immediate form instruction having at least one constant value encoded directly therein from the at least one register. The optimization results in an optimized sequence of target instructions, which when translated into a sequence of host instructions, is more efficiently executed by a host computing environment.

Abstract: A method is provided for recording a list of facilities available to a program executing on an information processing system. In such method a storage location and a length of data are defined for recording the list of facilities by a program being executed on the information processing system. An instruction is issued by the program for determining the available facilities and recording the list of available facilities in accordance with the defined storage location and data length. A processor executes the instruction to determine the available facilities and record the list of facilities in accordance with the defined storage location and defined data length. The recorded list of facilities can then be read by the first program.