Patents by Inventor Mike Sapozhnikov

Mike Sapozhnikov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11894296
    Abstract: An apparatus includes an integrated circuit package and a heatsink. The integrated circuit package includes a substrate, an integrated circuit, a first plurality of signal conductors, and a second plurality of signal conductors. The substrate includes a first surface and a second surface opposite the first surface. The integrated circuit is coupled to the first surface of the substrate. The first plurality of signal conductors are arranged along a periphery of the first surface of the substrate. The second plurality of signal conductors are arranged along a periphery of the second surface of the substrate. The heatsink includes a first portion positioned along the first surface of the substrate and a second portion positioned along the second surface of the substrate.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: February 6, 2024
    Assignee: Cisco Technology, Inc.
    Inventors: Mike Sapozhnikov, Sayed Ashraf Mamun, Tomer Osi, Amendra Koul, David Nozadze, Upendranadh R. Kareti, Joel R. Goergen
  • Publication number: 20230397343
    Abstract: The techniques described herein relate to an apparatus including: a support structure of an integrated circuit device; and an elongated cavity formed in the support structure of the integrated circuit device, wherein an interior of the elongated cavity is plated with a conductive material separated into a first power connection portion and a first ground connection portion.
    Type: Application
    Filed: September 12, 2022
    Publication date: December 7, 2023
    Inventors: Mike Sapozhnikov, Sayed Ashraf Mamun, D. Brice Achkir, David Nozadze, Amendra Koul, Upen Reddy Kareti
  • Publication number: 20230378677
    Abstract: A communication interconnect system is described. The system may include a co-packaged cables (CPC) tile with a slot formed from a first surface to slot surface at a first depth in the CPC tile and a plurality of channels formed between the slot surface and a second surface opposite the first surface. The system may also include a twinaxial cable with a pair of conductors positioned in the slot such that the pair of conductors are inserted in a pair of channels of the plurality of channels to establish an electrical connection between the twinaxial cable and the pair of channels. The system also includes a plurality of elastomer pins positioned in the plurality of channels adjacent to the second surface.
    Type: Application
    Filed: April 14, 2023
    Publication date: November 23, 2023
    Inventors: Mike SAPOZHNIKOV, Sayed Ashraf MAMUN, D. Brice ACHKIR, David NOZADZE, Amendra KOUL, Upendranadh R. KARETI
  • Patent number: 11781858
    Abstract: A method is provided that includes inspecting a layer of a printed circuit board through an inspection window comprising an opening formed in one or more other layers of the printed circuit board and identifying a location of a trace aligned with the inspection window, relative to a marker in a fiber bundle of a fiber weave to assess fiber weave skew.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: October 10, 2023
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Amendra Koul, Yaochao Yang, Mike Sapozhnikov, Joel Richard Goergen, Kartheek Nalla
  • Patent number: 11777239
    Abstract: Certain aspects of the present disclosure provide techniques for pinless interconnect for twinaxial cables to an IC. This includes a socket coupled to an integrated circuit (IC), a port structure coupled to the socket, and a ground connector inserted into the port structure. It further includes a twinaxial cable including a pair of conductors inserted through the ground connector to establish an electrical connection between the twinaxial cable and the IC.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: October 3, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Mike Sapozhnikov, Sayed Ashraf Mamun, Tomer Osi, Amendra Koul, David Nozadze, Upendranadh R. Kareti, Joel R. Goergen
  • Patent number: 11761755
    Abstract: In one embodiment, a method includes inspecting a fiber weave for use in a printed circuit board with an automated optical inspection tool and identifying a distance between fiber bundles in the fiber weave. The fiber weave comprises a plurality of the fiber bundles woven to form the fiber weave and a portion of the fiber bundles comprise markers and identifying a distance between the fiber bundles in the fiber weave comprises measuring a distance between the markers.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: September 19, 2023
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Amendra Koul, Yaochao Yang, Mike Sapozhnikov, Joel Richard Goergen, Kartheek Nalla
  • Publication number: 20230198639
    Abstract: Channel predictive behavior and fault analysis may be provided. A forward time value may be determined comprising a time a forward signal takes to travel from a transmitter over a channel to the receiver. Next, a reflected time value may be determined comprising a time a reflected signal takes to travel to the receiver. The reflected signal may be associated with the forward signal. A discontinuity may then be determined to exist on the channel based on the forward time value and the reflected time value. The reflected signal may be caused by the discontinuity and a high impedance or low impedance at the transmitter present after the forward signal is sent.
    Type: Application
    Filed: February 22, 2023
    Publication date: June 22, 2023
    Applicant: Cisco Technology, Inc.
    Inventors: Amendra Koul, David Nozadze, Mike Sapozhnikov, Joel Goergen, Arnav Shailesh Shah
  • Publication number: 20230104301
    Abstract: An apparatus includes a printed circuit board (PCB), and an integrated circuit (IC) package connected with the PCB. The IC package includes a package substrate, a die secured to the package substrate and including an integrated circuit, and a stiffener ring secured to the package substrate and surrounding so as to define a perimeter around the die. The stiffener ring increases a rigidity of the package substrate and delivers electrical power to the integrated circuit, where the stiffener ring includes a first conductive layer forming a power (PWR) plane for the integrated circuit, a second conductive layer forming a ground (GND) plane for the integrated circuit, and an insulating layer disposed between the first conductive layer and the second conductive layer.
    Type: Application
    Filed: October 4, 2021
    Publication date: April 6, 2023
    Inventors: Xiaohong Wu, Xing Wang, Mike Sapozhnikov, Sayed Ashraf Mamun, Tomer Osi, Joel Goergen
  • Patent number: 11606152
    Abstract: Channel predictive behavior and fault analysis may be provided. A forward time value may be determined comprising a time a forward signal takes to travel from a transmitter over a channel to the receiver. Next, a reflected time value may be determined comprising a time a reflected signal takes to travel to the receiver. The reflected signal may be associated with the forward signal. A discontinuity may then be determined to exist on the channel based on the forward time value and the reflected time value. The reflected signal may be caused by the discontinuity and a high impedance or low impedance at the transmitter present after the forward signal is sent.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: March 14, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Amendra Koul, David Nozadze, Mike Sapozhnikov, Joel Goergen, Arnav Shailesh Shah
  • Publication number: 20220393776
    Abstract: Channel predictive behavior and fault analysis may be provided. A forward time value may be determined comprising a time a forward signal takes to travel from a transmitter over a channel to the receiver. Next, a reflected time value may be determined comprising a time a reflected signal takes to travel to the receiver. The reflected signal may be associated with the forward signal. A discontinuity may then be determined to exist on the channel based on the forward time value and the reflected time value. The reflected signal may be caused by the discontinuity and a high impedance or low impedance at the transmitter present after the forward signal is sent.
    Type: Application
    Filed: June 8, 2021
    Publication date: December 8, 2022
    Applicant: Cisco Technology, Inc.
    Inventors: Amendra Koul, David Nozadze, Mike Sapozhnikov, Joel Goergen, Arnav Shailesh Shah
  • Publication number: 20220359366
    Abstract: An apparatus includes an integrated circuit package and a heatsink. The integrated circuit package includes a substrate, an integrated circuit, a first plurality of signal conductors, and a second plurality of signal conductors. The substrate includes a first surface and a second surface opposite the first surface. The integrated circuit is coupled to the first surface of the substrate. The first plurality of signal conductors are arranged along a periphery of the first surface of the substrate. The second plurality of signal conductors are arranged along a periphery of the second surface of the substrate. The heatsink includes a first portion positioned along the first surface of the substrate and a second portion positioned along the second surface of the substrate.
    Type: Application
    Filed: September 2, 2021
    Publication date: November 10, 2022
    Inventors: Mike SAPOZHNIKOV, Sayed Ashraf MAMUN, Tomer OSI, Amendra KOUL, David NOZADZE, Upendranadh R. KARETI, Joel R. GOERGEN
  • Publication number: 20220360005
    Abstract: Certain aspects of the present disclosure provide techniques for pinless interconnect for twinaxial cables to an IC. This includes a socket coupled to an integrated circuit (IC), a port structure coupled to the socket, and a ground connector inserted into the port structure. It further includes a twinaxial cable including a pair of conductors inserted through the ground connector to establish an electrical connection between the twinaxial cable and the IC.
    Type: Application
    Filed: March 4, 2022
    Publication date: November 10, 2022
    Inventors: Mike SAPOZHNIKOV, Sayed Ashraf MAMUN, Tomer OSI, Amendra KOUL, David NOZADZE, Upendranadh R. KARETI, Joel R. GOERGEN
  • Patent number: 11482802
    Abstract: An apparatus includes a printed circuit board (PCB). The PCB includes a plurality of through-holes extending through the PCB between a PCB first surface and a PCB second surface that opposes the PCB first surface, where each through-hole includes a via extending from the PCB first surface to a depth within the through-hole that is distanced from the PCB second surface. An integrated circuit surface mount is connected at the PCB first surface with vias of the through-holes, and a cable interconnect assembly is surface mount connected at the PCB second surface. The cable interconnect assembly includes a plurality of contact pins, each contact pin extending within a corresponding through-hole and having a sufficient dimension to engage and electrically connect with the via of the corresponding through-hole so as to facilitate exchange of an electrical signal between the integrated circuit and the cable interconnect assembly.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: October 25, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Jason Visneski, George Edward Curtis, Mike Sapozhnikov, Peter Gunadisastra, Joel Goergen
  • Patent number: 11425821
    Abstract: A printed circuit board (PCB) includes a plurality of layers disposed at different depths of the PCB, circuit components disposed at different layers of the PCB, and a plurality of temperature measurement sensors located at one or more layers of the PCB, where each temperature measurement sensor is associated with a corresponding circuit component. A measured temperature is obtained at an embedded temperature measurement sensor located at an embedded layer within the PCB, and the measured temperature is correlated with an electrical property of an embedded circuit component located at the same embedded layer within the PCB as the embedded temperature measurement sensor. A plurality of moisture measurement sensors can also be located at one or more layers of the PCB to facilitate a measured moisture with an electrical property of an embedded circuit component.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 23, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Amendra Koul, Mike Sapozhnikov, David Nozadze, Joel Goergen
  • Publication number: 20220181807
    Abstract: An apparatus includes a printed circuit board (PCB). The PCB includes a plurality of through-holes extending through the PCB between a PCB first surface and a PCB second surface that opposes the PCB first surface, where each through-hole includes a via extending from the PCB first surface to a depth within the through-hole that is distanced from the PCB second surface. An integrated circuit surface mount is connected at the PCB first surface with vias of the through-holes, and a cable interconnect assembly is surface mount connected at the PCB second surface. The cable interconnect assembly includes a plurality of contact pins, each contact pin extending within a corresponding through-hole and having a sufficient dimension to engage and electrically connect with the via of the corresponding through-hole so as to facilitate exchange of an electrical signal between the integrated circuit and the cable interconnect assembly.
    Type: Application
    Filed: May 28, 2021
    Publication date: June 9, 2022
    Inventors: Jason Visneski, George Edward Curtis, Mike Sapozhnikov, Peter Gunadisastra, Joel Goergen
  • Publication number: 20220128350
    Abstract: A method is provided that includes inspecting a layer of a printed circuit board through an inspection window comprising an opening formed in one or more other layers of the printed circuit board and identifying a location of a trace aligned with the inspection window, relative to a marker in a fiber bundle of a fiber weave to assess fiber weave skew.
    Type: Application
    Filed: January 11, 2022
    Publication date: April 28, 2022
    Inventors: Amendra Koul, Yaochao Yang, Mike Sapozhnikov, Joel Richard Goergen, Kartheek Nalla
  • Publication number: 20220120558
    Abstract: In one embodiment, a method includes inspecting a fiber weave for use in a printed circuit board with an automated optical inspection tool and identifying a distance between fiber bundles in the fiber weave. The fiber weave comprises a plurality of the fiber bundles woven to form the fiber weave and a portion of the fiber bundles comprise markers and identifying a distance between the fiber bundles in the fiber weave comprises measuring a distance between the markers.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 21, 2022
    Inventors: Amendra Koul, Yaochao Yang, Mike Sapozhnikov, Joel Richard Goergen, Kartheek Nalla
  • Patent number: 11293752
    Abstract: In one embodiment, a method includes inspecting a fiber weave for use in a printed circuit board with an automated optical inspection tool and identifying a distance between fiber bundles in the fiber weave. The fiber weave comprises a plurality of the fiber bundles woven to form the fiber weave and a portion of the fiber bundles comprise markers and identifying a distance between the fiber bundles in the fiber weave comprises measuring a distance between the markers.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: April 5, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Amendra Koul, Yaochao Yang, Mike Sapozhnikov, Joel Richard Goergen, Kartheek Nalla
  • Patent number: 11287245
    Abstract: In one embodiment, a method includes inspecting a layer of a printed circuit board through an inspection window comprising an opening formed in one or more other layers of the printed circuit board and identifying a location of a trace aligned with the inspection window, relative to a marker in a fiber bundle of a fiber weave to assess fiber weave skew.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: March 29, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Amendra Koul, Yaochao Yang, Mike Sapozhnikov, Joel Richard Goergen, Kartheek Nalla
  • Publication number: 20210059055
    Abstract: A printed circuit board (PCB) includes a plurality of layers disposed at different depths of the PCB, circuit components disposed at different layers of the PCB, and a plurality of temperature measurement sensors located at one or more layers of the PCB, where each temperature measurement sensor is associated with a corresponding circuit component. A measured temperature is obtained at an embedded temperature measurement sensor located at an embedded layer within the PCB, and the measured temperature is correlated with an electrical property of an embedded circuit component located at the same embedded layer within the PCB as the embedded temperature measurement sensor. A plurality of moisture measurement sensors can also be located at one or more layers of the PCB to facilitate a measured moisture with an electrical property of an embedded circuit component.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Amendra Koul, Mike Sapozhnikov, David Nozadze, Joel Goergen