Patents by Inventor Mike Sun

Mike Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8006106
    Abstract: A method and system for flexibly supplying power to a high-end graphics card is described. The graphics system includes the high-end graphics card and also a configurable power supply module, which is physically separated to the graphics card and connected to a power source external to the graphics system. The configurable power supply module converts a first voltage from the power source to a second voltage for the graphics card, wherein the second voltage satisfies a set of power supply specifications required by the graphics card.
    Type: Grant
    Filed: January 21, 2008
    Date of Patent: August 23, 2011
    Assignee: NVIDIA Corporation
    Inventor: Mike Sun
  • Patent number: 7755107
    Abstract: According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement-mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: July 13, 2010
    Assignee: Skyworks Solutions, Inc.
    Inventors: Peter J. Zampardi, Mike Sun
  • Publication number: 20100072517
    Abstract: According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement-mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET.
    Type: Application
    Filed: September 24, 2008
    Publication date: March 25, 2010
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventors: Peter J. Zampardi, Mike Sun
  • Publication number: 20090172236
    Abstract: A method and system for flexibly supplying power to a high-end graphics card is described. The graphics system includes the high-end graphics card and also a configurable power supply module, which is physically separated to the graphics card and connected to a power source external to the graphics system. The configurable power supply module converts a first voltage from the power source to a second voltage for the graphics card, wherein the second voltage satisfies a set of power supply specifications required by the graphics card.
    Type: Application
    Filed: January 21, 2008
    Publication date: July 2, 2009
    Inventor: Mike SUN
  • Publication number: 20070210340
    Abstract: A GaAs power transistor unit cell is provided with one of its transistor contacts on its bottom surface, and its other two transistor contacts on its frontside surface. In one arrangement, the GaAs power transistor unit cell has a N+ GaAs substrate that cooperates with an N? GaAs material to form a transistor collector. A collector contact is on a bottom surface of the collector, and a transistor base is provided on the collector. An emitter is arranged on the base. Accordingly, the collector contact is on the bottom of the unit cell, while a base contact and emitter contact are oriented to the frontside of the unit cell. It will be understood that the emitter and collector portions may be exchanged in other constructions. In use, the GaAs transistor unit cells are interconnected to form a GaAs power transistor, with the power transistor having externally available contacts. In one specific construction, a connection pad is provided on a laminate substrate.
    Type: Application
    Filed: March 10, 2006
    Publication date: September 13, 2007
    Inventors: Peter Zampardi, Mike Sun
  • Patent number: D772126
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: November 22, 2016
    Assignee: MaxTrac Suspension, LLC
    Inventor: Mike Sun
  • Patent number: D845842
    Type: Grant
    Filed: August 13, 2017
    Date of Patent: April 16, 2019
    Inventor: Mike Sun
  • Patent number: D864798
    Type: Grant
    Filed: August 13, 2017
    Date of Patent: October 29, 2019
    Inventor: Mike Sun
  • Patent number: D1090366
    Type: Grant
    Filed: October 6, 2023
    Date of Patent: August 26, 2025
    Inventor: Mike Sun